Synchronizer Entity Reference

Inherited by AxiLiteRingBuffer, AxiStreamFifoV2, AxiStreamFrameRateLimiter, AxiRingBuffer, AxiStreamDmaRingRead, AsyncGearbox, Debouncer, WatchDogRst, SynchronizerEdge, SynchronizerOneShotCnt, SynchronizerOneShotCntVector, Jesd204bRx, Jesd204bTx, Pgp3AxiL, Pgp3Tx, Pgp4Tx, Pgp4TxLite, PgpTxVcFifo, Saci2Coordinator, Saci2ToAxiLite, SaciAxiLiteMaster, SaciMaster2, SsiPrbsRx, Ad9249ReadoutGroup, Ad9249ReadoutGroup2, AxiAd9467Reg, Ad9681Readout, Ad9681ReadoutManual, AxiLtc2270Reg, Sgmii88E1111LvdsUltraScale, SgmiiDp83867LvdsUltraScale, Caui4GtyIpWrapper, TenGigEthRst, TenGigEthGth7Clk, TenGigEthGthUltraScaleRst, TenGigEthGtx7Clk, TenGigEthGtyUltraScaleRst, ClinkData, CoaXPressAxiL, GLinkDecoder, GLinkGtp7FixedLat, GLinkGtx7FixedLat, Pgp2bAxi, Pgp2bTx, Pgp2fcAlignmentController, Pgp2fcAxi, Pgp2fcTx, Pgp2fcGthUltra, Pgp2fcGtyUltra, SpiSlave, DeviceDna7Series, Gth7AutoPhaseAligner, Gth7RxRst, Gth7RxRstSeq, Gth7TxManualPhaseAligner, Gth7TxRst, Gtp7AutoPhaseAligner, Gtx7RxRst, and DeviceDnaUltraScale.

Entities
Synchronizer.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
OUT_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
STAGES_G	positive := 2
BYPASS_SYNC_G	boolean := false
INIT_G	slv := " 0 "

Ports
clk	in	sl
rst	in	sl := not RST_POLARITY_G
dataIn	in	sl
dataOut	out	sl

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/Synchronizer.vhd
• build/SRC_VHDL/surf/Synchronizer.vhd