CoaXPressAxiL Entity Reference

Inheritance diagram for CoaXPressAxiL:

Collaboration diagram for CoaXPressAxiL:

Entities
CoaXPressAxiL.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
CoaXPressPkg	Package <CoaXPressPkg>

Generics
TPD_G	time := 1 ns
NUM_LANES_G	positive := 1
STATUS_CNT_WIDTH_G	positive range 1 to 32 := 12
RX_FSM_CNT_WIDTH_G	positive range 1 to 24 := 16
AXIL_CLK_FREQ_G	real := 156 . 25E + 6
AXIS_CLK_FREQ_G	real := 156 . 25E + 6
AXIS_CONFIG_G	AxiStreamConfigType

Ports
gtRstAll	out	sl
txClk	in	sl
txRst	in	sl
txTrigInv	out	sl
txPulseWidth	out	slv ( 31 downto 0 )
txTrig	in	sl
swTrig	out	sl
txTrigDrop	in	sl
trigAck	in	sl
txLinkUp	in	sl
txLsRate	out	sl
txLsLaneEn	out	slv ( 3 downto 0 )
rxClk	in	slv ( NUM_LANES_G- 1 downto 0 )
rxRst	in	slv ( NUM_LANES_G- 1 downto 0 )
rxDispErr	in	slv ( NUM_LANES_G- 1 downto 0 )
rxDecErr	in	slv ( NUM_LANES_G- 1 downto 0 )
rxLinkUp	in	slv ( NUM_LANES_G- 1 downto 0 )
rxFsmRst	out	sl
rxNumberOfLane	out	slv ( 2 downto 0 )
rxOverflow	in	sl
rxFsmError	in	sl
cfgClk	in	sl
cfgRst	in	sl
configTimerSize	out	slv ( 31 downto 0 )
configErrResp	out	sl
configPktTag	out	sl
dataClk	in	sl
dataRst	in	sl
dataMaster	in	AxiStreamMasterType
dataSlave	in	AxiStreamSlaveType
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• protocols/coaxpress/core/rtl/CoaXPressAxiL.vhd