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AxiLitePkg Package Reference
Package >> AxiLitePkg

Functions

AxiLiteReadSlaveType   axiLiteReadSlaveEmptyInit ( rresp: in slv( 1 downto 0) AXI_RESP_OK_C , rdata: in slv( 31 downto 0) ( others => '0') )
AxiLiteWriteSlaveType   axiLiteWriteSlaveEmptyInit ( bresp: in slv( 1 downto 0) AXI_RESP_OK_C )
AxiLiteWriteMasterArray   axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteWriteMasterType   axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteReadMasterArray   axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteReadMasterType   axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteCrossbarMasterConfigArray   genAxiLiteConfig (
num: in positive
base: in slv( 31 downto 0)
baseBot: in integer range 1 to 32
addrBits: in integer range 0 to 31
)
AxiLiteReadMasterType   ite (
i: in boolean
t: in AxiLiteReadMasterType
e: in AxiLiteReadMasterType
)
AxiLiteReadSlaveType   ite (
i: in boolean
t: in AxiLiteReadSlaveType
e: in AxiLiteReadSlaveType
)
AxiLiteWriteMasterType   ite (
i: in boolean
t: in AxiLiteWriteMasterType
e: in AxiLiteWriteMasterType
)
AxiLiteWriteSlaveType   ite (
i: in boolean
t: in AxiLiteWriteSlaveType
e: in AxiLiteWriteSlaveType
)
AxiLiteReadSlaveType   axiLiteReadSlaveEmptyInit ( rresp: in slv( 1 downto 0) AXI_RESP_OK_C , rdata: in slv( 31 downto 0) ( others => '0') )
AxiLiteWriteSlaveType   axiLiteWriteSlaveEmptyInit ( bresp: in slv( 1 downto 0) AXI_RESP_OK_C )
AxiLiteWriteMasterArray   axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteWriteMasterType   axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteReadMasterArray   axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteReadMasterType   axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteCrossbarMasterConfigArray   genAxiLiteConfig (
num: in positive
base: in slv( 31 downto 0)
baseBot: in integer range 1 to 32
addrBits: in integer range 0 to 31
)
AxiLiteReadMasterType   ite (
i: in boolean
t: in AxiLiteReadMasterType
e: in AxiLiteReadMasterType
)
AxiLiteReadSlaveType   ite (
i: in boolean
t: in AxiLiteReadSlaveType
e: in AxiLiteReadSlaveType
)
AxiLiteWriteMasterType   ite (
i: in boolean
t: in AxiLiteWriteMasterType
e: in AxiLiteWriteMasterType
)
AxiLiteWriteSlaveType   ite (
i: in boolean
t: in AxiLiteWriteSlaveType
e: in AxiLiteWriteSlaveType
)

Procedures

  axiSlaveWaitWriteTxn(
signal axiWriteMaster: in AxiLiteWriteMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable writeEnable: inout sl
)
  axiSlaveWaitReadTxn(
signal axiReadMaster: in AxiLiteReadMasterType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable readEnable: inout sl
)
  axiSlaveWaitTxn(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: inout AxiLiteStatusType
)
  axiSlaveWriteResponse( variable axiWriteSlave: inout AxiLiteWriteSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
  axiSlaveReadResponse( variable axiReadSlave: inout AxiLiteReadSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
  axiSlaveRegister(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: inout slv
constAssign: in boolean false
constVal: in slv " 0 "
)
  axiSlaveRegister(
signal axiReadMaster: in AxiLiteReadMasterType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: in slv
)
  axiSlaveRegister(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: inout sl
constAssign: in boolean false
constVal: in sl ' 0 '
)
  axiSlaveRegister(
signal axiReadMaster: in AxiLiteReadMasterType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: in sl
)
  axiSlaveDefault(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C
extTxn: in sl ' 0 '
)
  axiSlaveWaitTxn(
variable ep: inout AxiLiteEndpointType
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: in AxiLiteWriteSlaveType
variable axiReadSlave: in AxiLiteReadSlaveType
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout slv
constVal: in slv
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout slv
)
  axiSlaveRegisterR(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: in slv
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout sl
constVal: in sl
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout sl
)
  axiSlaveRegisterR(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: in sl
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
regs: inout slv32Array
)
  axiSlaveRegisterR(
variable ep: inout AxiLiteEndpointType
addr: in slv
regs: in slv32Array
)
  axiWrDetect(
variable ep: inout AxiLiteEndpointType
addr: in slv
reg: inout sl
)
  axiRdDetect(
variable ep: inout AxiLiteEndpointType
addr: in slv
reg: inout sl
)
  axiSlaveDefault(
variable ep: inout AxiLiteEndpointType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C
extTxn: in sl ' 0 '
)
  axiLiteBusSimWrite(
signal axilClk: in sl
signal axilWriteMaster: out AxiLiteWriteMasterType
signal axilWriteSlave: in AxiLiteWriteSlaveType
addr: in slv ( 31 downto 0 )
data: in slv
debug: in boolean false
)
  axiLiteBusSimRead(
signal axilClk: in sl
signal axilReadMaster: out AxiLiteReadMasterType
signal axilReadSlave: in AxiLiteReadSlaveType
addr: in slv ( 31 downto 0 )
data: out slv
debug: in boolean false
)
  axiSlaveWaitWriteTxn(
signal axiWriteMaster: in AxiLiteWriteMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable writeEnable: inout sl
)
  axiSlaveWaitReadTxn(
signal axiReadMaster: in AxiLiteReadMasterType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable readEnable: inout sl
)
  axiSlaveWaitTxn(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: inout AxiLiteStatusType
)
  axiSlaveWriteResponse( variable axiWriteSlave: inout AxiLiteWriteSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
  axiSlaveReadResponse( variable axiReadSlave: inout AxiLiteReadSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
  axiSlaveRegister(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: inout slv
constAssign: in boolean false
constVal: in slv " 0 "
)
  axiSlaveRegister(
signal axiReadMaster: in AxiLiteReadMasterType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: in slv
)
  axiSlaveRegister(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: inout sl
constAssign: in boolean false
constVal: in sl ' 0 '
)
  axiSlaveRegister(
signal axiReadMaster: in AxiLiteReadMasterType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
addr: in slv
offset: in integer
reg: in sl
)
  axiSlaveDefault(
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
variable axiStatus: in AxiLiteStatusType
axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C
extTxn: in sl ' 0 '
)
  axiSlaveWaitTxn(
variable ep: inout AxiLiteEndpointType
signal axiWriteMaster: in AxiLiteWriteMasterType
signal axiReadMaster: in AxiLiteReadMasterType
variable axiWriteSlave: in AxiLiteWriteSlaveType
variable axiReadSlave: in AxiLiteReadSlaveType
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout slv
constVal: in slv
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout slv
)
  axiSlaveRegisterR(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: in slv
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout sl
constVal: in sl
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: inout sl
)
  axiSlaveRegisterR(
variable ep: inout AxiLiteEndpointType
addr: in slv
offset: in integer
reg: in sl
)
  axiSlaveRegister(
variable ep: inout AxiLiteEndpointType
addr: in slv
regs: inout slv32Array
)
  axiSlaveRegisterR(
variable ep: inout AxiLiteEndpointType
addr: in slv
regs: in slv32Array
)
  axiWrDetect(
variable ep: inout AxiLiteEndpointType
addr: in slv
reg: inout sl
)
  axiRdDetect(
variable ep: inout AxiLiteEndpointType
addr: in slv
reg: inout sl
)
  axiSlaveDefault(
variable ep: inout AxiLiteEndpointType
variable axiWriteSlave: inout AxiLiteWriteSlaveType
variable axiReadSlave: inout AxiLiteReadSlaveType
axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C
extTxn: in sl ' 0 '
)
  axiLiteBusSimWrite(
signal axilClk: in sl
signal axilWriteMaster: out AxiLiteWriteMasterType
signal axilWriteSlave: in AxiLiteWriteSlaveType
addr: in slv ( 31 downto 0 )
data: in slv
debug: in boolean false
)
  axiLiteBusSimRead(
signal axilClk: in sl
signal axilReadMaster: out AxiLiteReadMasterType
signal axilReadSlave: in AxiLiteReadSlaveType
addr: in slv ( 31 downto 0 )
data: out slv
debug: in boolean false
)

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
numeric_std 
StdRtlPkg  Package <StdRtlPkg>
TextUtilPkg  Package <TextUtilPkg>

Constants

AXI_RESP_OK_C  slv ( 1 downto 0 ) := " 00 "
AXI_RESP_EXOKAY_C  slv ( 1 downto 0 ) := " 01 "
AXI_RESP_SLVERR_C  slv ( 1 downto 0 ) := " 10 "
AXI_RESP_DECERR_C  slv ( 1 downto 0 ) := " 11 "
AXI_LITE_READ_MASTER_INIT_C  AxiLiteReadMasterType := ( araddr = > ( others = > ' 0 ' ) , arprot = > ( others = > ' 0 ' ) , arvalid = > ' 0 ' , rready = > ' 1 ' )
AXI_LITE_READ_SLAVE_INIT_C  AxiLiteReadSlaveType := ( arready = > ' 0 ' , rdata = > ( others = > ' 0 ' ) , rresp = > ( others = > ' 0 ' ) , rvalid = > ' 0 ' )
AXI_LITE_READ_SLAVE_EMPTY_OK_C  AxiLiteReadSlaveType := axiLiteReadSlaveEmptyInit ( rresp = > AXI_RESP_OK_C )
AXI_LITE_READ_SLAVE_EMPTY_SLVERR_C  AxiLiteReadSlaveType := axiLiteReadSlaveEmptyInit ( rresp = > AXI_RESP_SLVERR_C )
AXI_LITE_READ_SLAVE_EMPTY_DECERR_C  AxiLiteReadSlaveType := axiLiteReadSlaveEmptyInit ( rresp = > AXI_RESP_DECERR_C )
AXI_LITE_WRITE_MASTER_INIT_C  AxiLiteWriteMasterType := ( awaddr = > ( others = > ' 0 ' ) , awprot = > ( others = > ' 0 ' ) , awvalid = > ' 0 ' , wdata = > ( others = > ' 0 ' ) , wstrb = > ( others = > ' 1 ' ) , wvalid = > ' 0 ' , bready = > ' 1 ' )
AXI_LITE_WRITE_SLAVE_INIT_C  AxiLiteWriteSlaveType := ( awready = > ' 0 ' , wready = > ' 0 ' , bresp = > ( others = > ' 0 ' ) , bvalid = > ' 0 ' )
AXI_LITE_WRITE_SLAVE_EMPTY_OK_C  AxiLiteWriteSlaveType := axiLiteWriteSlaveEmptyInit ( bresp = > AXI_RESP_OK_C )
AXI_LITE_WRITE_SLAVE_EMPTY_SLVERR_C  AxiLiteWriteSlaveType := axiLiteWriteSlaveEmptyInit ( bresp = > AXI_RESP_SLVERR_C )
AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C  AxiLiteWriteSlaveType := axiLiteWriteSlaveEmptyInit ( bresp = > AXI_RESP_DECERR_C )
AXI_LITE_STATUS_INIT_C  AxiLiteStatusType := ( writeEnable = > ' 0 ' , readEnable = > ' 0 ' )
AXI_LITE_ENDPOINT_INIT_C  AxiLiteEndpointType := ( axiReadMaster = > AXI_LITE_READ_MASTER_INIT_C , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteMaster = > AXI_LITE_WRITE_MASTER_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axiStatus = > AXI_LITE_STATUS_INIT_C )
AXI_LITE_REQ_INIT_C  AxiLiteReqType := ( request = > ' 0 ' , rnw = > ' 1 ' , address = > ( others = > ' 0 ' ) , wrData = > ( others = > ' 0 ' ) )
AXI_LITE_ACK_INIT_C  AxiLiteAckType := ( done = > ' 0 ' , resp = > ( others = > ' 0 ' ) , rdData = > ( others = > ' 0 ' ) )
AXIL_XBAR_CFG_DEFAULT_C  AxiLiteCrossbarMasterConfigArray ( 0 to 3 ) := ( 0 = > ( baseAddr = > X " 00000000 " , addrBits = > 16 , connectivity = > X " FFFF " ) , 1 = > ( baseAddr = > X " 00010000 " , addrBits = > 16 , connectivity = > X " FFFF " ) , 2 = > ( baseAddr = > X " 00020000 " , addrBits = > 16 , connectivity = > X " FFFF " ) , 3 = > ( baseAddr = > X " 00030000 " , addrBits = > 16 , connectivity = > X " FFFF " ) )

Types

AxiLiteReadMasterArray  array ( natural range <> ) of AxiLiteReadMasterType
AxiLiteReadSlaveArray  array ( natural range <> ) of AxiLiteReadSlaveType
AxiLiteWriteMasterArray  array ( natural range <> ) of AxiLiteWriteMasterType
AxiLiteWriteSlaveArray  array ( natural range <> ) of AxiLiteWriteSlaveType

Subtypes

AxiLiteCrossbarMasterConfigArray  array ( natural range <> ) of AxiLiteCrossbarMasterConfigType

Records

AxiLiteReadMasterType 
AxiLiteReadSlaveType 
AxiLiteWriteMasterType 
AxiLiteWriteSlaveType 
AxiLiteStatusType 
AxiLiteEndpointType 
AxiLiteReqType 
AxiLiteAckType 
AxiLiteCrossbarMasterConfigType 
The documentation for this design unit was generated from the following files: