AxiLitePkg Package Body Reference

Package Body >> AxiLitePkg

Functions
AxiLiteReadSlaveType	axiLiteReadSlaveEmptyInit ( rresp: in slv( 1 downto 0) AXI_RESP_OK_C , rdata: in slv( 31 downto 0) ( others => '0') )
AxiLiteWriteSlaveType	axiLiteWriteSlaveEmptyInit ( bresp: in slv( 1 downto 0) AXI_RESP_OK_C )
AxiLiteReadMasterType	axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteReadMasterArray	axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteWriteMasterType	axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteWriteMasterArray	axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteCrossbarMasterConfigArray	genAxiLiteConfig ( num: in positive base: in slv( 31 downto 0) baseBot: in integer range 1 to 32 addrBits: in integer range 0 to 31 )
AxiLiteReadMasterType	ite ( i: in boolean t: in AxiLiteReadMasterType e: in AxiLiteReadMasterType )
AxiLiteReadSlaveType	ite ( i: in boolean t: in AxiLiteReadSlaveType e: in AxiLiteReadSlaveType )
AxiLiteWriteMasterType	ite ( i: in boolean t: in AxiLiteWriteMasterType e: in AxiLiteWriteMasterType )
AxiLiteWriteSlaveType	ite ( i: in boolean t: in AxiLiteWriteSlaveType e: in AxiLiteWriteSlaveType )
AxiLiteReadSlaveType	axiLiteReadSlaveEmptyInit ( rresp: in slv( 1 downto 0) AXI_RESP_OK_C , rdata: in slv( 31 downto 0) ( others => '0') )
AxiLiteWriteSlaveType	axiLiteWriteSlaveEmptyInit ( bresp: in slv( 1 downto 0) AXI_RESP_OK_C )
AxiLiteReadMasterType	axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteReadMasterArray	axiReadMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteWriteMasterType	axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigType )
AxiLiteWriteMasterArray	axiWriteMasterInit ( constant config: in AxiLiteCrossbarMasterConfigArray )
AxiLiteCrossbarMasterConfigArray	genAxiLiteConfig ( num: in positive base: in slv( 31 downto 0) baseBot: in integer range 1 to 32 addrBits: in integer range 0 to 31 )
AxiLiteReadMasterType	ite ( i: in boolean t: in AxiLiteReadMasterType e: in AxiLiteReadMasterType )
AxiLiteReadSlaveType	ite ( i: in boolean t: in AxiLiteReadSlaveType e: in AxiLiteReadSlaveType )
AxiLiteWriteMasterType	ite ( i: in boolean t: in AxiLiteWriteMasterType e: in AxiLiteWriteMasterType )
AxiLiteWriteSlaveType	ite ( i: in boolean t: in AxiLiteWriteSlaveType e: in AxiLiteWriteSlaveType )

Procedures
	axiSlaveWaitWriteTxn( signal axiWriteMaster: in AxiLiteWriteMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable writeEnable: inout sl )
	axiSlaveWaitReadTxn( signal axiReadMaster: in AxiLiteReadMasterType variable axiReadSlave: inout AxiLiteReadSlaveType variable readEnable: inout sl )
	axiSlaveWaitTxn( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: inout AxiLiteStatusType )
	axiSlaveWriteResponse( variable axiWriteSlave: inout AxiLiteWriteSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
	axiSlaveReadResponse( variable axiReadSlave: inout AxiLiteReadSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
	axiSlaveRegister( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: inout slv constAssign: in boolean false constVal: in slv " 0 " )
	axiSlaveRegister( signal axiReadMaster: in AxiLiteReadMasterType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: in slv )
	axiSlaveRegister( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: inout sl constAssign: in boolean false constVal: in sl ' 0 ' )
	axiSlaveRegister( signal axiReadMaster: in AxiLiteReadMasterType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: in sl )
	axiSlaveDefault( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C extTxn: in sl ' 0 ' )
	axiSlaveWaitTxn( variable ep: inout AxiLiteEndpointType signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: in AxiLiteWriteSlaveType variable axiReadSlave: in AxiLiteReadSlaveType )
	axiSlaveRegisterLegacy( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv constVal: in slv )
	axiSlaveRegisterLegacy( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv constVal: in slv )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv )
	axiSlaveRegisterR( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: in slv )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout sl constVal: in sl )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout sl )
	axiSlaveRegisterR( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: in sl )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv regs: inout slv32Array )
	axiSlaveRegisterR( variable ep: inout AxiLiteEndpointType addr: in slv regs: in slv32Array )
	axiWrDetect( variable ep: inout AxiLiteEndpointType addr: in slv reg: inout sl )
	axiRdDetect( variable ep: inout AxiLiteEndpointType addr: in slv reg: inout sl )
	axiSlaveDefault( variable ep: inout AxiLiteEndpointType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C extTxn: in sl ' 0 ' )
	axiLiteBusSimWrite( signal axilClk: in sl signal axilWriteMaster: out AxiLiteWriteMasterType signal axilWriteSlave: in AxiLiteWriteSlaveType addr: in slv ( 31 downto 0 ) data: in slv debug: in boolean false )
	axiLiteBusSimRead( signal axilClk: in sl signal axilReadMaster: out AxiLiteReadMasterType signal axilReadSlave: in AxiLiteReadSlaveType addr: in slv ( 31 downto 0 ) data: out slv debug: in boolean false )
	axiSlaveWaitWriteTxn( signal axiWriteMaster: in AxiLiteWriteMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable writeEnable: inout sl )
	axiSlaveWaitReadTxn( signal axiReadMaster: in AxiLiteReadMasterType variable axiReadSlave: inout AxiLiteReadSlaveType variable readEnable: inout sl )
	axiSlaveWaitTxn( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: inout AxiLiteStatusType )
	axiSlaveWriteResponse( variable axiWriteSlave: inout AxiLiteWriteSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
	axiSlaveReadResponse( variable axiReadSlave: inout AxiLiteReadSlaveType , axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C )
	axiSlaveRegister( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: inout slv constAssign: in boolean false constVal: in slv " 0 " )
	axiSlaveRegister( signal axiReadMaster: in AxiLiteReadMasterType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: in slv )
	axiSlaveRegister( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: inout sl constAssign: in boolean false constVal: in sl ' 0 ' )
	axiSlaveRegister( signal axiReadMaster: in AxiLiteReadMasterType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType addr: in slv offset: in integer reg: in sl )
	axiSlaveDefault( signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType variable axiStatus: in AxiLiteStatusType axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C extTxn: in sl ' 0 ' )
	axiSlaveWaitTxn( variable ep: inout AxiLiteEndpointType signal axiWriteMaster: in AxiLiteWriteMasterType signal axiReadMaster: in AxiLiteReadMasterType variable axiWriteSlave: in AxiLiteWriteSlaveType variable axiReadSlave: in AxiLiteReadSlaveType )
	axiSlaveRegisterLegacy( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv constVal: in slv )
	axiSlaveRegisterLegacy( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv constVal: in slv )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout slv )
	axiSlaveRegisterR( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: in slv )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout sl constVal: in sl )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: inout sl )
	axiSlaveRegisterR( variable ep: inout AxiLiteEndpointType addr: in slv offset: in integer reg: in sl )
	axiSlaveRegister( variable ep: inout AxiLiteEndpointType addr: in slv regs: inout slv32Array )
	axiSlaveRegisterR( variable ep: inout AxiLiteEndpointType addr: in slv regs: in slv32Array )
	axiWrDetect( variable ep: inout AxiLiteEndpointType addr: in slv reg: inout sl )
	axiRdDetect( variable ep: inout AxiLiteEndpointType addr: in slv reg: inout sl )
	axiSlaveDefault( variable ep: inout AxiLiteEndpointType variable axiWriteSlave: inout AxiLiteWriteSlaveType variable axiReadSlave: inout AxiLiteReadSlaveType axiResp: in slv ( 1 downto 0 ) AXI_RESP_OK_C extTxn: in sl ' 0 ' )
	axiLiteBusSimWrite( signal axilClk: in sl signal axilWriteMaster: out AxiLiteWriteMasterType signal axilWriteSlave: in AxiLiteWriteSlaveType addr: in slv ( 31 downto 0 ) data: in slv debug: in boolean false )
	axiLiteBusSimRead( signal axilClk: in sl signal axilReadMaster: out AxiLiteReadMasterType signal axilReadSlave: in AxiLiteReadSlaveType addr: in slv ( 31 downto 0 ) data: out slv debug: in boolean false )

---

The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLitePkg.vhd
• build/SRC_VHDL/surf/AxiLitePkg.vhd