PgpTxVcFifo Entity Reference

Inheritance diagram for PgpTxVcFifo:

Collaboration diagram for PgpTxVcFifo:

Entities
PgpTxVcFifo.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
INT_PIPE_STAGES_G	natural := 0
PIPE_STAGES_G	natural := 1
VALID_THOLD_G	positive := 1
VALID_BURST_MODE_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
GEN_SYNC_FIFO_G	boolean := false
FIFO_ADDR_WIDTH_G	positive := 9
CASCADE_SIZE_G	positive := 1
APP_AXI_CONFIG_G	AxiStreamConfigType
PHY_AXI_CONFIG_G	AxiStreamConfigType

Ports
axisClk	in	sl
axisRst	in	sl
axisMaster	in	AxiStreamMasterType
axisSlave	out	AxiStreamSlaveType
pgpClk	in	sl
pgpRst	in	sl
rxlinkReady	in	sl
txlinkReady	in	sl
pgpTxMaster	out	AxiStreamMasterType
pgpTxSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/PgpTxVcFifo.vhd
• protocols/pgp/shared/PgpTxVcFifo.vhd