PgpTxVcFifo.mapping Architecture Reference

Architecture >> PgpTxVcFifo::mapping

Signals
sMaster	AxiStreamMasterType
sSlave	AxiStreamSlaveType
master	AxiStreamMasterType
ctrl	AxiStreamCtrlType
linkReady	sl
flushEn	sl
axisReset	sl
pgpReset	sl

Instantiations
u_flushsync	Synchronizer <Entity Synchronizer>
u_axisrst	RstPipeline <Entity RstPipeline>
u_pgprst	RstPipeline <Entity RstPipeline>
u_axistreampipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_flush	AxiStreamFlush <Entity AxiStreamFlush>
u_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_flushsync	Synchronizer <Entity Synchronizer>
u_axisrst	RstPipeline <Entity RstPipeline>
u_pgprst	RstPipeline <Entity RstPipeline>
u_axistreampipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_flush	AxiStreamFlush <Entity AxiStreamFlush>
u_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/PgpTxVcFifo.vhd
• protocols/pgp/shared/PgpTxVcFifo.vhd