AxiStreamPipeline Entity Reference

Inheritance diagram for AxiStreamPipeline:

Entities
AxiStreamPipeline.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SIDE_BAND_WIDTH_G	positive := 1
PIPE_STAGES_G	natural := 0

Ports
axisClk	in	sl
axisRst	in	sl
sAxisMaster	in	AxiStreamMasterType
sSideBand	in	slv ( SIDE_BAND_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
sAxisSlave	out	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
mSideBand	out	slv ( SIDE_BAND_WIDTH_G- 1 downto 0 )
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamPipeline.vhd
• build/SRC_VHDL/surf/AxiStreamPipeline.vhd