AxiStreamPipeline.rtl Architecture Reference

Architecture >> AxiStreamPipeline::rtl

Processes
comb	( axisRst , mAxisSlave , r , sAxisMaster , sSideBand )
seq	( axisClk , axisRst )
comb	( axisRst , mAxisSlave , r , sAxisMaster , sSideBand )
seq	( axisClk , axisRst )

Constants
PIPE_STAGES_C	natural := PIPE_STAGES_G+ 1
REG_INIT_C	RegType := ( sAxisSlave = > AXI_STREAM_SLAVE_INIT_C , mAxisMaster = > ( others = > AXI_STREAM_MASTER_INIT_C ) , mSideBand = > ( others = > ( others = > ' 0 ' ) ) )

Types
SideBandArray	array ( natural range <> ) of slv ( SIDE_BAND_WIDTH_G- 1 downto 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamPipeline.vhd
• build/SRC_VHDL/surf/AxiStreamPipeline.vhd