Inherits AxiStreamGearbox, FifoCascade, SynchronizerVector, Synchronizer, and AxiStreamPipeline.
Inherited by AxiStreamFifoV2IpIntegrator, AxiStreamBatchingFifo, AxiStreamRingBuffer, AxiStreamResizeTb, AxiRingBuffer, AxiStreamDmaRingRead, AxiStreamDmaRingWrite, Caui4GtyIpWrapper, EthMacRxImportGmii, EthMacTxCsum, EthMacTxExportXgmii, EthMacTxFifo, IpV4EngineTb, EthMacRxRoCEv2, EthMacTxRoCEv2, UdpEngineDhcp, ClinkFraming, ClinkUart, CoaXPressRx, CoaXPressTx, HtspRxFifo, HtspTxFifo, HtspCoreTb, HtspCaui4GtyTb, pgp_test, Pgp2bLaneWrapper, Pgp2fcLane_tb, Pgp2fcLaneWrapper, Pgp3Tb, Pgp4RxProtocol, PgpRxVcFifo, PgpTxVcFifo, RssiCore, SaltTx, AxiLiteSrpV0, SrpV0AxiLite, SrpV3AxiLite, SrpV3Core, SsiAxiLiteMaster, SsiCmdMaster, SsiIncrementingTx, SsiResizeFifoEofeTb, SsiResizeFifoEofeWrapper, SsiSem, and DmaXvcWrapper.
Collaboration diagram for AxiStreamFifoV2:Entities | |
| AxiStreamFifoV2.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiStreamPkg | Package <AxiStreamPkg> |
Generics | |
| TPD_G | time := 1 ns |
| RST_POLARITY_G | sl := ' 1 ' |
| RST_ASYNC_G | boolean := false |
| INT_PIPE_STAGES_G | natural range 0 to 16 := 0 |
| PIPE_STAGES_G | natural range 0 to 16 := 1 |
| SLAVE_READY_EN_G | boolean := true |
| VALID_THOLD_G | integer range 0 to ( 2 ** 24 ) := 1 |
| VALID_BURST_MODE_G | boolean := false |
| GEN_SYNC_FIFO_G | boolean := false |
| FIFO_ADDR_WIDTH_G | integer range 4 to 48 := 9 |
| FIFO_FIXED_THRESH_G | boolean := true |
| FIFO_PAUSE_THRESH_G | integer range 1 to ( 2 ** 24 ) := 1 |
| SYNTH_MODE_G | string := " inferred " |
| MEMORY_TYPE_G | string := " block " |
| INT_WIDTH_SELECT_G | string := " WIDE " |
| INT_DATA_WIDTH_G | natural range 1 to AXI_STREAM_MAX_TKEEP_WIDTH_C := 16 |
| LAST_FIFO_ADDR_WIDTH_G | integer range 0 to 48 := 0 |
| CASCADE_PAUSE_SEL_G | integer range 0 to ( 2 ** 24 ) := 0 |
| CASCADE_SIZE_G | integer range 1 to ( 2 ** 24 ) := 1 |
| SLAVE_AXI_CONFIG_G | AxiStreamConfigType |
| MASTER_AXI_CONFIG_G | AxiStreamConfigType |
Ports | ||
| sAxisClk | in | sl |
| sAxisRst | in | sl |
| sAxisMaster | in | AxiStreamMasterType |
| sAxisSlave | out | AxiStreamSlaveType |
| sAxisCtrl | out | AxiStreamCtrlType := AXI_STREAM_CTRL_INIT_C |
| fifoPauseThresh | in | slv ( FIFO_ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 1 ' ) |
| fifoWrCnt | out | slv ( FIFO_ADDR_WIDTH_G- 1 downto 0 ) |
| fifoFull | out | sl |
| mAxisClk | in | sl |
| mAxisRst | in | sl |
| mAxisMaster | out | AxiStreamMasterType |
| mAxisSlave | in | AxiStreamSlaveType |
| mTLastTUser | out | slv ( 7 downto 0 ) |
The documentation for this design unit was generated from the following file:
- axi/axi-stream/rtl/AxiStreamFifoV2.vhd
