SsiResizeFifoEofeWrapper Entity Reference

Inheritance diagram for SsiResizeFifoEofeWrapper:

Collaboration diagram for SsiResizeFifoEofeWrapper:

Entities
SsiResizeFifoEofeWrapper.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
SLAVE_DATA_BYTES_G	positive range 1 to 64 := 8
MASTER_DATA_BYTES_G	positive range 1 to 64 := 8
SLAVE_TKEEP_MODE_G	natural range 0 to 2 := 0
MASTER_TKEEP_MODE_G	natural range 0 to 2 := 0
SLAVE_TUSER_MODE_G	natural range 0 to 3 := 0
MASTER_TUSER_MODE_G	natural range 0 to 3 := 0
SLAVE_TUSER_BITS_G	positive range 2 to 8 := 4
MASTER_TUSER_BITS_G	positive range 2 to 8 := 4

Ports
AXIS_ACLK	in	sl
AXIS_ARESETN	in	sl
S_AXIS_TVALID	in	sl
S_AXIS_TDATA	in	slv ( 511 downto 0 )
S_AXIS_TKEEP	in	slv ( 63 downto 0 )
S_AXIS_TLAST	in	sl
S_AXIS_TDEST	in	slv ( 3 downto 0 )
S_AXIS_EOFE	in	sl
S_AXIS_TREADY	out	sl
M_AXIS_TVALID	out	sl
M_AXIS_TDATA	out	slv ( 511 downto 0 )
M_AXIS_TKEEP	out	slv ( 63 downto 0 )
M_AXIS_TLAST	out	sl
M_AXIS_TDEST	out	slv ( 3 downto 0 )
M_AXIS_EOFE	out	sl
M_AXIS_TREADY	in	sl

---

The documentation for this design unit was generated from the following file:

• protocols/ssi/wrappers/SsiResizeFifoEofeWrapper.vhd