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AxiStreamBatchingFifo Entity Reference
Inheritance diagram for AxiStreamBatchingFifo: Collaboration diagram for AxiStreamBatchingFifo:Entities | |
| AxiStreamBatchingFifo.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| AxiStreamPkg | Package <AxiStreamPkg> |
| AxiLitePkg | Package <AxiLitePkg> |
Generics | |
| TPD_G | time := 1 ns |
| FIFO_ADDR_WIDTH_G | integer range 4 to 48 := 9 |
| SLAVE_AXI_CONFIG_G | AxiStreamConfigType |
| MASTER_AXI_CONFIG_G | AxiStreamConfigType |
Ports | ||
| axilClk | in | sl |
| axilRst | in | sl |
| sAxilWriteMaster | in | AxiLiteWriteMasterType |
| sAxilWriteSlave | out | AxiLiteWriteSlaveType |
| sAxilReadMaster | in | AxiLiteReadMasterType |
| sAxilReadSlave | out | AxiLiteReadSlaveType |
| sAxisClk | in | sl |
| sAxisRst | in | sl |
| sAxisMaster | in | AxiStreamMasterType |
| sAxisSlave | out | AxiStreamSlaveType |
| mAxisClk | in | sl |
| mAxisRst | in | sl |
| mAxisMaster | out | AxiStreamMasterType |
| mAxisSlave | in | AxiStreamSlaveType |
The documentation for this design unit was generated from the following file:
- axi/axi-stream/rtl/AxiStreamBatchingFifo.vhd
