Architecture >> AxiStreamBatchingFifo::rtl

Processes
comb_axil	( axilRst , batchSizeAxiL , rAxilReadSlave , rAxilWriteSlave , sAxilReadMaster , sAxilWriteMaster )
seq_axil	( axilClk )
comb	( axisMasterFifo , axisMasterSync , axisSlaveFifo , axisSlaveSync , batchSize , combAxisSlave , r )
seq	( mAxisClk )

Constants
REG_INIT_C	RegType := ( frameBatched = > ( others = > ' 0 ' ) , frameToSend = > ( others = > ' 0 ' ) , sending = > ' 0 ' )

Signals
batchSizeAxiL	slv ( 31 downto 0 )
batchSizeAxiLin	slv ( 31 downto 0 )
batchSize	slv ( 31 downto 0 )
axisMasterSync	AxiStreamMasterType
axisSlaveSync	AxiStreamSlaveType
axisMasterFifo	AxiStreamMasterType
axisSlaveFifo	AxiStreamSlaveType
r	RegType := REG_INIT_C
rin	RegType
rAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
rAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
rinAxilWriteSlave	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_INIT_C
rinAxilReadSlave	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_INIT_C
combAxisMaster	AxiStreamMasterType
combAxisSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_axis_cdc	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_batchsize_cdc	SynchronizerFifo <Entity SynchronizerFifo>
u_data_fifo	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_output_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>

The documentation for this design unit was generated from the following file:

Processes

Constants