SynchronizerFifo Entity Reference

Inheritance diagram for SynchronizerFifo:

Collaboration diagram for SynchronizerFifo:

Entities
SynchronizerFifo.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
COMMON_CLK_G	boolean := false
MEMORY_TYPE_G	string := " distributed "
SYNC_STAGES_G	integer range 3 to ( 2 ** 24 ) := 3
PIPE_STAGES_G	natural range 0 to 16 := 0
DATA_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 16
ADDR_WIDTH_G	integer range 2 to 48 := 4
INIT_G	slv := " 0 "

Ports
rst	in	sl := not RST_POLARITY_G
wr_clk	in	sl
wr_en	in	sl := ' 1 '
din	in	slv ( DATA_WIDTH_G- 1 downto 0 )
rd_clk	in	sl
rd_en	in	sl := ' 1 '
valid	out	sl
dout	out	slv ( DATA_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SynchronizerFifo.vhd
• build/SRC_VHDL/surf/SynchronizerFifo.vhd