SynchronizerFifo.rtl Architecture Reference

Architecture >> SynchronizerFifo::rtl

Constants
INIT_C	slv ( DATA_WIDTH_G- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( DATA_WIDTH_G ) , INIT_G )

Instantiations
fifoasync_1	FifoAsync <Entity FifoAsync>
fifoasync_1	FifoAsync <Entity FifoAsync>

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SynchronizerFifo.vhd
• build/SRC_VHDL/surf/SynchronizerFifo.vhd