AxiStreamFifoV2IpIntegrator Entity Reference

Inheritance diagram for AxiStreamFifoV2IpIntegrator:

Collaboration diagram for AxiStreamFifoV2IpIntegrator:

Entities
AxiStreamFifoV2IpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
S_INTERFACENAME	string := " S_AXIS "
S_HAS_TLAST	natural range 0 to 1 := 1
S_HAS_TKEEP	natural range 0 to 1 := 1
S_HAS_TSTRB	natural range 0 to 1 := 0
S_HAS_TREADY	natural range 0 to 1 := 1
S_TUSER_WIDTH	natural range 1 to 8 := 2
S_TID_WIDTH	natural range 1 to 8 := 1
S_TDEST_WIDTH	natural range 1 to 8 := 1
S_TDATA_NUM_BYTES	natural range 1 to 128 := 1
M_INTERFACENAME	string := " M_AXIS "
M_HAS_TLAST	natural range 0 to 1 := 1
M_HAS_TKEEP	natural range 0 to 1 := 1
M_HAS_TSTRB	natural range 0 to 1 := 0
M_HAS_TREADY	natural range 0 to 1 := 1
M_TUSER_WIDTH	natural range 1 to 8 := 2
M_TID_WIDTH	natural range 1 to 8 := 1
M_TDEST_WIDTH	natural range 1 to 8 := 1
M_TDATA_NUM_BYTES	natural range 1 to 128 := 1
RST_ASYNC	boolean := false
INT_PIPE_STAGES	natural range 0 to 16 := 0
PIPE_STAGES	natural range 0 to 16 := 1
VALID_BURST_MODE	boolean := false
VALID_THOLD	integer range 0 to ( 2 ** 24 ) := 1
GEN_SYNC_FIFO	boolean := false
FIFO_ADDR_WIDTH	integer range 4 to 48 := 9
FIFO_FIXED_THRESH	boolean := true
FIFO_PAUSE_THRESH	integer range 1 to ( 2 ** 24 ) := 1
SYNTH_MODE	string := " inferred "
MEMORY_TYPE	string := " block "
INT_WIDTH_SELECT	string := " WIDE "
INT_DATA_WIDTH	natural range 1 to 16 := 16
LAST_FIFO_ADDR_WIDTH	integer range 0 to 48 := 0
CASCADE_PAUSE_SEL	integer range 0 to ( 2 ** 24 ) := 0
CASCADE_SIZE	integer range 1 to ( 2 ** 24 ) := 1

Ports
S_AXIS_ACLK	in	std_logic := ' 0 '
S_AXIS_ARESETN	in	std_logic := ' 0 '
S_AXIS_TVALID	in	std_logic := ' 0 '
S_AXIS_TDATA	in	std_logic_vector ( ( 8 * S_TDATA_NUM_BYTES ) - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TSTRB	in	std_logic_vector ( S_TDATA_NUM_BYTES- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TKEEP	in	std_logic_vector ( S_TDATA_NUM_BYTES- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TLAST	in	std_logic := ' 0 '
S_AXIS_TDEST	in	std_logic_vector ( S_TDEST_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TID	in	std_logic_vector ( S_TID_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TUSER	in	std_logic_vector ( S_TUSER_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TREADY	out	std_logic
M_AXIS_ACLK	in	std_logic := ' 0 '
M_AXIS_ARESETN	in	std_logic := ' 0 '
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( ( 8 * M_TDATA_NUM_BYTES ) - 1 downto 0 )
M_AXIS_TSTRB	out	std_logic_vector ( M_TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( M_TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TDEST	out	std_logic_vector ( M_TDEST_WIDTH- 1 downto 0 )
M_AXIS_TID	out	std_logic_vector ( M_TID_WIDTH- 1 downto 0 )
M_AXIS_TUSER	out	std_logic_vector ( M_TUSER_WIDTH- 1 downto 0 )
M_AXIS_TREADY	in	std_logic := ' 1 '
fifoPauseThresh	in	std_logic_vector ( FIFO_ADDR_WIDTH- 1 downto 0 ) := ( others = > ' 1 ' )
fifoWrCnt	out	std_logic_vector ( FIFO_ADDR_WIDTH- 1 downto 0 )
fifoFull	out	std_logic
sAxisPause	out	std_logic
sAxisOverflow	out	std_logic
sAxisIdle	out	std_logic
mTLastTUser	out	std_logic_vector ( 7 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/ip_integrator/AxiStreamFifoV2IpIntegrator.vhd
• build/SRC_VHDL/surf/AxiStreamFifoV2IpIntegrator.vhd