Architecture >> AxiStreamFifoV2IpIntegrator::mapping

Constants
S_AXI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > ite ( S_HAS_TSTRB = 1 , true , false ) , TDATA_BYTES_C = > S_TDATA_NUM_BYTES , TDEST_BITS_C = > S_TDEST_WIDTH , TID_BITS_C = > S_TID_WIDTH , TKEEP_MODE_C = > ite ( S_HAS_TKEEP = 1 , TKEEP_NORMAL_C , TKEEP_FIXED_C ) , TUSER_BITS_C = > S_TUSER_WIDTH , TUSER_MODE_C = > TUSER_NORMAL_C )
M_AXI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > ite ( M_HAS_TSTRB = 1 , true , false ) , TDATA_BYTES_C = > M_TDATA_NUM_BYTES , TDEST_BITS_C = > M_TDEST_WIDTH , TID_BITS_C = > M_TID_WIDTH , TKEEP_MODE_C = > ite ( M_HAS_TKEEP = 1 , TKEEP_NORMAL_C , TKEEP_FIXED_C ) , TUSER_BITS_C = > M_TUSER_WIDTH , TUSER_MODE_C = > TUSER_NORMAL_C )

Signals
sAxisClk	sl := ' 0 '
sAxisRst	sl := ' 0 '
sAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
sAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
sAxisCtrl	AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C
mAxisClk	sl := ' 0 '
mAxisRst	sl := ' 0 '
mAxisMaster	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
mAxisSlave	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Instantiations
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_axistreamfifov2	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>
u_shimlayerslave	SlaveAxiStreamIpIntegrator <Entity SlaveAxiStreamIpIntegrator>
u_axistreamfifov2	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_shimlayermaster	MasterAxiStreamIpIntegrator <Entity MasterAxiStreamIpIntegrator>

The documentation for this design unit was generated from the following files:

Constants

Signals