MasterAxiStreamIpIntegrator Entity Reference

Inherits RstSync.

Inherited by AxiStreamBatchingFifoIpIntegrator, AxiStreamCombinerIpIntegrator, AxiStreamCompactIpIntegrator, AxiStreamConcatIpIntegrator, AxiStreamDeMuxIpIntegrator, AxiStreamFifoV2IpIntegrator, AxiStreamFlushIpIntegrator, AxiStreamFrameRateLimiterIpIntegrator, AxiStreamGearboxIpIntegrator, AxiStreamGearboxPackIpIntegrator, AxiStreamGearboxUnpackIpIntegrator, AxiStreamMuxIpIntegrator, AxiStreamPipelineIpIntegrator, AxiStreamPrbsFlowCtrlIpIntegrator, AxiStreamRepeaterIpIntegrator, AxiStreamResizeIpIntegrator, AxiStreamRingBufferIpIntegrator, AxiStreamScatterGatherIpIntegrator, AxiStreamShiftIpIntegrator, AxiStreamSplitterIpIntegrator, AxiStreamTapIpIntegrator, AxiStreamTrailerAppendIpIntegrator, AxiStreamTrailerRemoveIpIntegrator, MasterAxiStreamTerminateIpIntegrator, AxiStreamDemuxMuxTb, AxiStreamGearboxTb, AxiRingBufferIpIntegrator, AxiStreamDmaReadIpIntegrator, AxiStreamDmaRingReadIpIntegrator, AxiStreamDmaRingWriteIpIntegrator, AxiStreamDmaV2FifoIpIntegrator, AxiStreamDmaV2ReadIpIntegrator, FirFilterMultiChannelCacheTestWrapper, FirFilterMultiChannelTestWrapper, EthMacCrcAxiStreamWrapperRecv, EthMacCrcAxiStreamWrapperSend, RoceEngineWrapper, EventFrameSequencerTb, EventFrameSequencerWrapper, Pgp2bLaneWrapper, Pgp2fcLaneWrapper, Pgp3CoreWrapper, Pgp4CoreLiteTb, Pgp4CoreTb, Pgp4CoreLiteWrapper, Pgp4CoreWrapper, PgpRxVcFifoWrapper, PgpTxVcFifoWrapper, and SrpV3AxiWrapper.

Collaboration diagram for MasterAxiStreamIpIntegrator:

Entities
MasterAxiStreamIpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
INTERFACENAME	string := " M_AXIS "
HAS_TLAST	natural range 0 to 1 := 1
HAS_TKEEP	natural range 0 to 1 := 1
HAS_TSTRB	natural range 0 to 1 := 0
HAS_TREADY	natural range 0 to 1 := 1
TUSER_WIDTH	natural range 1 to 8 := 2
TID_WIDTH	natural range 1 to 8 := 1
TDEST_WIDTH	natural range 1 to 8 := 1
TDATA_NUM_BYTES	natural range 1 to 128 := 1

Ports
M_AXIS_ACLK	in	std_logic := ' 0 '
M_AXIS_ARESETN	in	std_logic := ' 0 '
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( ( 8 * TDATA_NUM_BYTES ) - 1 downto 0 )
M_AXIS_TSTRB	out	std_logic_vector ( TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TDEST	out	std_logic_vector ( TDEST_WIDTH- 1 downto 0 )
M_AXIS_TID	out	std_logic_vector ( TID_WIDTH- 1 downto 0 )
M_AXIS_TUSER	out	std_logic_vector ( TUSER_WIDTH- 1 downto 0 )
M_AXIS_TREADY	in	std_logic := ' 1 '
axisClk	out	sl
axisRst	out	sl
axisMaster	in	AxiStreamMasterType := AXI_STREAM_MASTER_INIT_C
axisSlave	out	AxiStreamSlaveType

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The documentation for this design unit was generated from the following file:

• axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd