Architecture >> MasterAxiStreamIpIntegrator::mapping
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X_INTERFACE_INFO | string |
X_INTERFACE_PARAMETER | string |
X_INTERFACE_INFO | signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TVALID " |
X_INTERFACE_INFO | signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TLAST " |
X_INTERFACE_INFO | signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TDATA " |
X_INTERFACE_INFO | signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TKEEP " |
X_INTERFACE_INFO | signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TREADY " |
X_INTERFACE_PARAMETER | signal is " XIL_INTERFACENAME " & INTERFACENAME& " , " & " LAYERED_METADATA undef , " & " HAS_TLAST " & integer ' image ( HAS_TLAST ) & " , " & " HAS_TKEEP " & integer ' image ( HAS_TKEEP ) & " , " & " HAS_TSTRB " & integer ' image ( HAS_TSTRB ) & " , " & " HAS_TREADY " & integer ' image ( HAS_TREADY ) & " , " & " TUSER_WIDTH " & integer ' image ( TUSER_WIDTH ) & " , " & " TID_WIDTH " & integer ' image ( TID_WIDTH ) & " , " & " TDEST_WIDTH " & integer ' image ( TDEST_WIDTH ) & " , " & " TDATA_NUM_BYTES " & integer ' image ( TDATA_NUM_BYTES ) |
X_INTERFACE_INFO | signal is " xilinx.com : signal : reset : 1.0 RST. " & INTERFACENAME& " _ARESETN RST " |
X_INTERFACE_PARAMETER | signal is " XIL_INTERFACENAME RST. " & INTERFACENAME& " _ARESETN , " & " POLARITY ACTIVE_LOW " |
X_INTERFACE_INFO | signal is " xilinx.com : signal : clock : 1.0 CLK. " & INTERFACENAME& " _ACLK CLK " |
X_INTERFACE_PARAMETER | signal is " XIL_INTERFACENAME CLK. " & INTERFACENAME& " _ACLK , " & " ASSOCIATED_BUSIF " & INTERFACENAME& " , " & " ASSOCIATED_RESET " & INTERFACENAME& " _ARESETN " |
The documentation for this design unit was generated from the following files:
- axi/axi-stream/ip_integrator/MasterAxiStreamIpIntegrator.vhd
- build/SRC_VHDL/surf/MasterAxiStreamIpIntegrator.vhd