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SlaveAxiStreamIpIntegrator Entity Reference

Inherits RstSync.

Inherited by AxiStreamBatchingFifoIpIntegrator, AxiStreamCombinerIpIntegrator, AxiStreamCompactIpIntegrator, AxiStreamConcatIpIntegrator, AxiStreamDeMuxIpIntegrator, AxiStreamFifoV2IpIntegrator, AxiStreamFlushIpIntegrator, AxiStreamFrameRateLimiterIpIntegrator, AxiStreamGearboxIpIntegrator, AxiStreamGearboxPackIpIntegrator, AxiStreamGearboxUnpackIpIntegrator, AxiStreamMonAxiLIpIntegrator, AxiStreamMonIpIntegrator, AxiStreamMuxIpIntegrator, AxiStreamPipelineIpIntegrator, AxiStreamPrbsFlowCtrlIpIntegrator, AxiStreamRepeaterIpIntegrator, AxiStreamResizeIpIntegrator, AxiStreamScatterGatherIpIntegrator, AxiStreamShiftIpIntegrator, AxiStreamSplitterIpIntegrator, AxiStreamTapIpIntegrator, AxiStreamTrailerAppendIpIntegrator, AxiStreamTrailerRemoveIpIntegrator, SlaveAxiStreamTerminateIpIntegrator, AxiStreamDemuxMuxTb, AxiStreamGearboxTb, AxiStreamDmaRingReadIpIntegrator, AxiStreamDmaRingWriteIpIntegrator, AxiStreamDmaV2FifoIpIntegrator, AxiStreamDmaV2WriteIpIntegrator, AxiStreamDmaWriteIpIntegrator, FirFilterMultiChannelCacheTestWrapper, FirFilterMultiChannelTestWrapper, EthMacCrcAxiStreamWrapperRecv, EthMacCrcAxiStreamWrapperSend, RoceEngineWrapper, EventFrameSequencerTb, EventFrameSequencerWrapper, Pgp2bLaneWrapper, Pgp2fcLaneWrapper, Pgp3CoreWrapper, Pgp4CoreLiteTb, Pgp4CoreTb, Pgp4CoreLiteWrapper, Pgp4CoreWrapper, PgpRxVcFifoWrapper, PgpTxVcFifoWrapper, and SrpV3AxiWrapper.

+ Collaboration diagram for SlaveAxiStreamIpIntegrator:

Entities

SlaveAxiStreamIpIntegrator.mapping  architecture
 

Libraries

ieee 
surf 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
AxiStreamPkg  Package <AxiStreamPkg>

Generics

INTERFACENAME  string := " S_AXIS "
HAS_TLAST  natural range 0 to 1 := 1
HAS_TKEEP  natural range 0 to 1 := 1
HAS_TSTRB  natural range 0 to 1 := 0
HAS_TREADY  natural range 0 to 1 := 1
TUSER_WIDTH  natural range 1 to 8 := 2
TID_WIDTH  natural range 1 to 8 := 1
TDEST_WIDTH  natural range 1 to 8 := 1
TDATA_NUM_BYTES  natural range 1 to 128 := 1

Ports

S_AXIS_ACLK   in   std_logic := ' 0 '
S_AXIS_ARESETN   in   std_logic := ' 0 '
S_AXIS_TVALID   in   std_logic := ' 0 '
S_AXIS_TDATA   in   std_logic_vector ( ( 8 * TDATA_NUM_BYTES ) - 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TSTRB   in   std_logic_vector ( TDATA_NUM_BYTES- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TKEEP   in   std_logic_vector ( TDATA_NUM_BYTES- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TLAST   in   std_logic := ' 0 '
S_AXIS_TDEST   in   std_logic_vector ( TDEST_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TID   in   std_logic_vector ( TID_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TUSER   in   std_logic_vector ( TUSER_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_AXIS_TREADY   out   std_logic
axisClk   out   sl
axisRst   out   sl
axisMaster   out   AxiStreamMasterType
axisSlave   in   AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

The documentation for this design unit was generated from the following file: