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SlaveAxiStreamIpIntegrator.mapping Architecture Reference
Architecture >> SlaveAxiStreamIpIntegrator::mapping

Constants

AXIS_CONFIG_C  AxiStreamConfigType := ( TSTRB_EN_C = > ( HAS_TSTRB = 1 ) , TDATA_BYTES_C = > TDATA_NUM_BYTES , TDEST_BITS_C = > TDEST_WIDTH , TID_BITS_C = > TID_WIDTH , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > TUSER_WIDTH , TUSER_MODE_C = > TUSER_NORMAL_C )

Signals

S_AXIS_Master  AxiStreamMasterType := axiStreamMasterInit ( AXIS_CONFIG_C )
S_AXIS_Slave  AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C

Attributes

X_INTERFACE_INFO  string
X_INTERFACE_PARAMETER  string
X_INTERFACE_INFO  signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TVALID "
X_INTERFACE_INFO  signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TLAST "
X_INTERFACE_INFO  signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TDATA "
X_INTERFACE_INFO  signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TKEEP "
X_INTERFACE_INFO  signal is " xilinx.com : interface : axis : 1.0 " & INTERFACENAME& " TREADY "
X_INTERFACE_PARAMETER  signal is " XIL_INTERFACENAME " & INTERFACENAME& " , " & " LAYERED_METADATA undef , " & " HAS_TLAST " & integer ' image ( HAS_TLAST ) & " , " & " HAS_TKEEP " & integer ' image ( HAS_TKEEP ) & " , " & " HAS_TSTRB " & integer ' image ( HAS_TSTRB ) & " , " & " HAS_TREADY " & integer ' image ( HAS_TREADY ) & " , " & " TUSER_WIDTH " & integer ' image ( TUSER_WIDTH ) & " , " & " TID_WIDTH " & integer ' image ( TID_WIDTH ) & " , " & " TDEST_WIDTH " & integer ' image ( TDEST_WIDTH ) & " , " & " TDATA_NUM_BYTES " & integer ' image ( TDATA_NUM_BYTES )
X_INTERFACE_INFO  signal is " xilinx.com : signal : reset : 1.0 RST. " & INTERFACENAME& " _ARESETN RST "
X_INTERFACE_PARAMETER  signal is " XIL_INTERFACENAME RST. " & INTERFACENAME& " _ARESETN , " & " POLARITY ACTIVE_LOW "
X_INTERFACE_INFO  signal is " xilinx.com : signal : clock : 1.0 CLK. " & INTERFACENAME& " _ACLK CLK "
X_INTERFACE_PARAMETER  signal is " XIL_INTERFACENAME CLK. " & INTERFACENAME& " _ACLK , " & " ASSOCIATED_BUSIF " & INTERFACENAME& " , " & " ASSOCIATED_RESET " & INTERFACENAME& " _ARESETN "

Instantiations

u_rstsync  RstSync <Entity RstSync>
u_rstsync  RstSync <Entity RstSync>
The documentation for this design unit was generated from the following files: