SrpV0AxiLite Entity Reference

Inheritance diagram for SrpV0AxiLite:

Collaboration diagram for SrpV0AxiLite:

Entities
SrpV0AxiLite.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RESP_THOLD_G	integer range 0 to ( 2 ** 24 ) := 1
SLAVE_READY_EN_G	boolean := false
EN_32BIT_ADDR_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
GEN_SYNC_FIFO_G	boolean := false
FIFO_ADDR_WIDTH_G	integer range 4 to 48 := 9
FIFO_PAUSE_THRESH_G	integer range 1 to ( 2 ** 24 ) := 2 ** 8
AXI_STREAM_CONFIG_G	AxiStreamConfigType

Ports
sAxisClk	in	sl
sAxisRst	in	sl := ' 0 '
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
sAxisCtrl	out	AxiStreamCtrlType
mAxisClk	in	sl
mAxisRst	in	sl := ' 0 '
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType
axiLiteClk	in	sl
axiLiteRst	in	sl
mAxiLiteWriteMaster	out	AxiLiteWriteMasterType
mAxiLiteWriteSlave	in	AxiLiteWriteSlaveType
mAxiLiteReadMaster	out	AxiLiteReadMasterType
mAxiLiteReadSlave	in	AxiLiteReadSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SrpV0AxiLite.vhd
• protocols/srp/rtl/SrpV0AxiLite.vhd