Architecture >> AxiStreamFifoV2::rtl

Processes
PROCESS_4	( fifoPFullVec , fifoPauseThresh , fifoWrCount , sAxisClk , sAxisRst )
PROCESS_5	( fifoReadLast , fifoValidInt , mAxisClk , mAxisRst )
PROCESS_6	( mAxisClk , mAxisRst )
PROCESS_85	( fifoPFullVec , fifoPauseThresh , fifoWrCount , sAxisClk , sAxisRst )
PROCESS_86	( fifoReadLast , fifoValidInt , mAxisClk , mAxisRst )
PROCESS_87	( mAxisClk , mAxisRst )

Constants
LAST_FIFO_ADDR_WIDTH_C	integer range 4 to 48 := ite ( LAST_FIFO_ADDR_WIDTH_G< 4 , FIFO_ADDR_WIDTH_G , LAST_FIFO_ADDR_WIDTH_G )
FIFO_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > SLAVE_AXI_CONFIG_G.TSTRB_EN_Cand MASTER_AXI_CONFIG_G.TSTRB_EN_C , TDATA_BYTES_C = > ite ( INT_WIDTH_SELECT_G = " CUSTOM " , INT_DATA_WIDTH_G , ite ( INT_WIDTH_SELECT_G = " WIDE " , ite ( SLAVE_AXI_CONFIG_G.TDATA_BYTES_C> MASTER_AXI_CONFIG_G.TDATA_BYTES_C , SLAVE_AXI_CONFIG_G.TDATA_BYTES_C , MASTER_AXI_CONFIG_G.TDATA_BYTES_C ) , ite ( SLAVE_AXI_CONFIG_G.TDATA_BYTES_C> MASTER_AXI_CONFIG_G.TDATA_BYTES_C , MASTER_AXI_CONFIG_G.TDATA_BYTES_C , SLAVE_AXI_CONFIG_G.TDATA_BYTES_C ) ) ) , TDEST_BITS_C = > ite ( SLAVE_AXI_CONFIG_G.TDEST_BITS_C> MASTER_AXI_CONFIG_G.TDEST_BITS_C , MASTER_AXI_CONFIG_G.TDEST_BITS_C , SLAVE_AXI_CONFIG_G.TDEST_BITS_C ) , TID_BITS_C = > ite ( SLAVE_AXI_CONFIG_G.TID_BITS_C> MASTER_AXI_CONFIG_G.TID_BITS_C , MASTER_AXI_CONFIG_G.TID_BITS_C , SLAVE_AXI_CONFIG_G.TID_BITS_C ) , TUSER_BITS_C = > ite ( SLAVE_AXI_CONFIG_G.TUSER_BITS_C> MASTER_AXI_CONFIG_G.TUSER_BITS_C , MASTER_AXI_CONFIG_G.TUSER_BITS_C , SLAVE_AXI_CONFIG_G.TUSER_BITS_C ) , TKEEP_MODE_C = > SLAVE_AXI_CONFIG_G.TKEEP_MODE_C , TUSER_MODE_C = > SLAVE_AXI_CONFIG_G.TUSER_MODE_C )
FIFO_BITS_C	integer := getSlvSize ( FIFO_CONFIG_C )
FIFO_USER_BITS_C	integer := FIFO_CONFIG_C.TUSER_BITS_C

Signals
fifoWriteMaster	AxiStreamMasterType
fifoWriteSlave	AxiStreamSlaveType
fifoReadMaster	AxiStreamMasterType
fifoReadSlave	AxiStreamSlaveType
fifoDin	slv ( FIFO_BITS_C- 1 downto 0 )
fifoWrite	sl
fifoWriteLast	sl
fifoWriteUser	slv ( maximum ( FIFO_USER_BITS_C- 1 , 0 ) downto 0 ) := ( others = > ' 0 ' )
fifoWrCount	slv ( FIFO_ADDR_WIDTH_G- 1 downto 0 )
fifoRdCount	slv ( FIFO_ADDR_WIDTH_G- 1 downto 0 )
fifoAFull	sl
fifoReady	sl
fifoPFull	sl
fifoPFullVec	slv ( CASCADE_SIZE_G- 1 downto 0 )
fifoDout	slv ( FIFO_BITS_C- 1 downto 0 )
fifoRead	sl
fifoReadLast	sl
fifoReadUser	slv ( maximum ( FIFO_USER_BITS_C- 1 , 0 ) downto 0 )
fifoValidInt	sl
fifoValid	sl
fifoValidLast	sl
fifoInFrame	sl
burstEn	sl
burstLast	sl
burstCnt	natural range 0 to VALID_THOLD_G := 0
firstCycle	sl
sideBand	Slv8Array ( 1 downto 0 )
axisMaster	AxiStreamMasterType
axisSlave	AxiStreamSlaveType

Instantiations
u_slaveresize	AxiStreamGearbox <Entity AxiStreamGearbox>
u_fifo	FifoCascade <Entity FifoCascade>
u_lastfifo	FifoCascade <Entity FifoCascade>
u_masterresize	AxiStreamGearbox <Entity AxiStreamGearbox>
synchronizer_1	Synchronizer <Entity Synchronizer>
u_pipe	AxiStreamPipeline <Entity AxiStreamPipeline>
u_slaveresize	AxiStreamGearbox <Entity AxiStreamGearbox>
u_fifo	FifoCascade <Entity FifoCascade>
u_lastfifo	FifoCascade <Entity FifoCascade>
u_masterresize	AxiStreamGearbox <Entity AxiStreamGearbox>
synchronizer_1	Synchronizer <Entity Synchronizer>
u_pipe	AxiStreamPipeline <Entity AxiStreamPipeline>

The documentation for this design unit was generated from the following files:

Processes

Constants