FifoCascade Entity Reference

Inheritance diagram for FifoCascade:

Collaboration diagram for FifoCascade:

Entities
FifoCascade.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
CASCADE_SIZE_G	integer range 1 to ( 2 ** 24 ) := 1
LAST_STAGE_ASYNC_G	boolean := true
GEN_SYNC_FIFO_G	boolean := false
FWFT_EN_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
SYNC_STAGES_G	integer range 3 to ( 2 ** 24 ) := 3
PIPE_STAGES_G	natural range 0 to 16 := 0
DATA_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 16
ADDR_WIDTH_G	integer range 4 to 48 := 4
INIT_G	slv := " 0 "
FULL_THRES_G	integer range 1 to ( 2 ** 24 ) := 1
EMPTY_THRES_G	integer range 1 to ( 2 ** 24 ) := 1

Ports
rst	in	sl := ' 0 '
wr_clk	in	sl
wr_en	in	sl := ' 0 '
din	in	slv ( DATA_WIDTH_G- 1 downto 0 )
wr_data_count	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
wr_ack	out	sl
overflow	out	sl
prog_full	out	sl
almost_full	out	sl
full	out	sl
not_full	out	sl
progFullVec	out	slv ( CASCADE_SIZE_G- 1 downto 0 )
rd_clk	in	sl
rd_en	in	sl := ' 0 '
dout	out	slv ( DATA_WIDTH_G- 1 downto 0 )
rd_data_count	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
valid	out	sl
underflow	out	sl
prog_empty	out	sl
almost_empty	out	sl
empty	out	sl

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/FifoCascade.vhd
• build/SRC_VHDL/surf/FifoCascade.vhd