FifoCascade.mapping Architecture Reference

Architecture >> FifoCascade::mapping

Constants
GEN_SYNC_FIFO_FIRST_C	boolean := ite ( LAST_STAGE_ASYNC_G , true , GEN_SYNC_FIFO_G )
GEN_SYNC_FIFO_LAST_C	boolean := ite ( LAST_STAGE_ASYNC_G , GEN_SYNC_FIFO_G , true )
CASCADE_SIZE_C	integer := ite ( ( CASCADE_SIZE_G = 1 ) , 0 , ( CASCADE_SIZE_G- 2 ) )

Types
FifoDataType	( CASCADE_SIZE_C downto 0 ) slv ( ( DATA_WIDTH_G- 1 ) downto 0 )

Signals
progFull	sl
cascadeClk	sl
readJump	slv ( CASCADE_SIZE_C downto 0 )
validJump	slv ( CASCADE_SIZE_C downto 0 )
AFullJump	slv ( CASCADE_SIZE_C downto 0 )
dataJump	FifoDataType

Instantiations
fifo_1xstage	Fifo <Entity Fifo>
fifo_first_stage	Fifo <Entity Fifo>
fifo_middle_stage	Fifo <Entity Fifo>
fifo_last_stage	Fifo <Entity Fifo>
fifo_1xstage	Fifo <Entity Fifo>
fifo_first_stage	Fifo <Entity Fifo>
fifo_middle_stage	Fifo <Entity Fifo>
fifo_last_stage	Fifo <Entity Fifo>

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/FifoCascade.vhd
• build/SRC_VHDL/surf/FifoCascade.vhd