SynchronizerVector Entity Reference

Inheritance diagram for SynchronizerVector:

Entities
SynchronizerVector.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
OUT_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
STAGES_G	positive := 2
BYPASS_SYNC_G	boolean := false
WIDTH_G	integer := 16
INIT_G	slv := " 0 "

Ports
clk	in	sl
rst	in	sl := not RST_POLARITY_G
dataIn	in	slv ( WIDTH_G- 1 downto 0 )
dataOut	out	slv ( WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SynchronizerVector.vhd
• build/SRC_VHDL/surf/SynchronizerVector.vhd