SsiIncrementingTx Entity Reference

Inheritance diagram for SsiIncrementingTx:

Collaboration diagram for SsiIncrementingTx:

Entities
SsiIncrementingTx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
MEMORY_TYPE_G	string := " block "
GEN_SYNC_FIFO_G	boolean := false
CASCADE_SIZE_G	natural range 1 to ( 2 ** 24 ) := 1
FIFO_ADDR_WIDTH_G	natural range 4 to 48 := 9
FIFO_PAUSE_THRESH_G	natural range 1 to ( 2 ** 24 ) := 2 ** 8
PRBS_SEED_SIZE_G	natural range 32 to 128 := 32
PRBS_TAPS_G	NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
MASTER_AXI_STREAM_CONFIG_G	AxiStreamConfigType
MASTER_AXI_PIPE_STAGES_G	natural range 0 to 16 := 0

Ports
mAxisClk	in	sl
mAxisRst	in	sl
mAxisSlave	in	AxiStreamSlaveType
mAxisMaster	out	AxiStreamMasterType
locClk	in	sl
locRst	in	sl := ' 0 '
trig	in	sl := ' 1 '
packetLength	in	slv ( 31 downto 0 ) := X " FFFFFFFF "
busy	out	sl
tDest	in	slv ( 7 downto 0 ) := X " 00 "
tId	in	slv ( 7 downto 0 ) := X " 00 "

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiIncrementingTx.vhd
• protocols/ssi/rtl/SsiIncrementingTx.vhd