SsiIncrementingTx.rtl Architecture Reference

Architecture >> SsiIncrementingTx::rtl

Processes
comb	( locRst , packetLength , r , tDest , tId , trig , txAxisSlave )
seq	( locClk , locRst )
comb	( locRst , packetLength , r , tDest , tId , trig , txAxisSlave )
seq	( locClk , locRst )

Constants
PRBS_BYTES_C	natural := PRBS_SEED_SIZE_G/ 8
PRBS_SSI_CONFIG_C	AxiStreamConfigType := ssiAxiStreamConfig ( PRBS_BYTES_C , TKEEP_NORMAL_C )
REG_INIT_C	RegType := ( ' 1 ' , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , AXI_STREAM_MASTER_INIT_C , IDLE_S )

Types
StateType	( IDLE_S , SEED_RAND_S , LENGTH_S , DATA_S , LAST_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
txAxisMaster	AxiStreamMasterType
txAxisSlave	AxiStreamSlaveType

Records
RegType

Instantiations
axistreamfifo_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
axistreamfifo_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiIncrementingTx.vhd
• protocols/ssi/rtl/SsiIncrementingTx.vhd