AxiStreamDmaRingRead Entity Reference

Inheritance diagram for AxiStreamDmaRingRead:

Collaboration diagram for AxiStreamDmaRingRead:

Entities
AxiStreamDmaRingRead.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>
AxiStreamDmaRingPkg	Package <AxiStreamDmaRingPkg>

Generics
TPD_G	time := 1 ns
BUFFERS_G	natural range 2 to 64 := 64
BURST_SIZE_BYTES_G	natural range 4 to 2 ** 17 := 4096
SSI_OUTPUT_G	boolean := false
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
AXI_BURST_G	slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G	slv ( 3 downto 0 ) := " 0011 "
AXI_STREAM_READY_EN_G	boolean := true
AXI_STREAM_CONFIG_G	AxiStreamConfigType
AXI_READ_CONFIG_G	AxiConfigType

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	out	AxiLiteReadMasterType
axilReadSlave	in	AxiLiteReadSlaveType
axilWriteMaster	out	AxiLiteWriteMasterType
axilWriteSlave	in	AxiLiteWriteSlaveType
statusClk	in	sl
statusRst	in	sl
statusMaster	in	AxiStreamMasterType
statusSlave	out	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
dataMaster	out	AxiStreamMasterType
dataSlave	in	AxiStreamSlaveType
dataCtrl	in	AxiStreamCtrlType := AXI_STREAM_CTRL_UNUSED_C
axiClk	in	sl
axiRst	in	sl
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd
• build/SRC_VHDL/surf/AxiStreamDmaRingRead.vhd