AxiStreamDmaRingPkg Package Reference

Package >> AxiStreamDmaRingPkg

Functions
slv	getBufferAddr ( baseAddr: in slv( 31 downto 0) busIndex: in integer range 0 to 7 buf: in slv( 5 downto 0) ( others => '0') high: in sl '0' )
slv	getBufferAddr ( baseAddr: in slv( 31 downto 0) busIndex: in integer range 0 to 7 buf: in integer range 0 to 63 0 high: in sl '0' )
slv	getBufferAddr ( baseAddr: in slv( 31 downto 0) busIndex: in integer range 0 to 7 buf: in slv( 5 downto 0) ( others => '0') high: in sl '0' )
slv	getBufferAddr ( baseAddr: in slv( 31 downto 0) busIndex: in integer range 0 to 7 buf: in integer range 0 to 63 0 high: in sl '0' )

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Constants
AXIL_MASTERS_C	integer := 6
START_AXIL_C	integer := 0
END_AXIL_C	integer := 1
NEXT_AXIL_C	integer := 2
TRIG_AXIL_C	integer := 3
MODE_AXIL_C	integer := 4
STATUS_AXIL_C	integer := 5
EMPTY_C	integer := 0
FULL_C	integer := 1
DONE_C	integer := 2
TRIGGERED_C	integer := 3
ERROR_C	integer := 4
ENABLED_C	integer := 0
DONE_WHEN_FULL_C	integer := 1
INIT_C	integer := 2
SOFT_TRIGGER_C	integer := 3
INIT_BYTE_C	integer := INIT_C/ 8
BUFFER_CLEAR_OFFSET_C	slv ( 7 downto 0 ) := X " 18 "
DMA_RING_STATUS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > 1 , TDEST_BITS_C = > 0 , TID_BITS_C = > 0 , TKEEP_MODE_C = > TKEEP_FIXED_C , TUSER_BITS_C = > 1 , TUSER_MODE_C = > TUSER_NONE_C )

Subtypes
BURST_SIZE_C	integer range 11 downto 8
FST_C	integer range 31 downto 16
STATUS_TDEST_C	integer range 7 downto 4
FAT_C	integer range 31 downto 16

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDmaRingPkg.vhd
• build/SRC_VHDL/surf/AxiStreamDmaRingPkg.vhd