AxiStreamDmaRingRead.rtl Architecture Reference

Architecture >> AxiStreamDmaRingRead::rtl

Processes
comb	( axilAck , axilRst , dmaAck , intStatusMaster , r )
seq	( axilClk )

Constants
DMA_ADDR_LOW_C	integer := log2 ( BURST_SIZE_BYTES_G )
REG_INIT_C	RegType := ( startAddr = > ( others = > ' 0 ' ) , endAddr = > ( others = > ' 0 ' ) , mode = > ( others = > ' 0 ' ) , state = > START_LOW_S , axilReq = > AXI_LITE_REQ_INIT_C , dmaReq = > AXI_READ_DMA_REQ_INIT_C , intStatusSlave = > AXI_STREAM_SLAVE_INIT_C )

Types
StateType	( START_LOW_S , START_HIGH_S , END_LOW_S , END_HIGH_S , MODE_S , DMA_REQ_S , CLEAR_HIGH_S , CLEAR_LOW_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
intStatusMaster	AxiStreamMasterType
axilAck	AxiLiteAckType
dmaAck	AxiReadDmaAckType
dmaReqAxi	AxiReadDmaReqType
dmaAckAxi	AxiReadDmaAckType

Records
RegType

Instantiations
u_axilitemaster_1	AxiLiteMaster <Entity AxiLiteMaster>
u_axistreamdmaread_1	AxiStreamDmaRead <Entity AxiStreamDmaRead>
u_synchronizer_req	Synchronizer <Entity Synchronizer>
u_synchronizerfifo_reqdata	SynchronizerVector <Entity SynchronizerVector>
u_synchronizer_ack	Synchronizer <Entity Synchronizer>
u_synchronizerfifo_ack	SynchronizerVector <Entity SynchronizerVector>
u_axistreamfifo_status	AxiStreamFifoV2 <Entity AxiStreamFifoV2>

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The documentation for this design unit was generated from the following file:

• axi/dma/rtl/v1/AxiStreamDmaRingRead.vhd