AxiStreamDmaRead Entity Reference

Inheritance diagram for AxiStreamDmaRead:

Collaboration diagram for AxiStreamDmaRead:

Entities
AxiStreamDmaRead.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns
AXIS_READY_EN_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType
AXI_CONFIG_G	AxiConfigType
AXI_BURST_G	slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G	slv ( 3 downto 0 ) := " 1111 "
SW_CACHE_EN_G	boolean := false
PIPE_STAGES_G	natural := 1
PEND_THRESH_G	natural := 0
BYP_SHIFT_G	boolean := false

Ports
axiClk	in	sl
axiRst	in	sl
dmaReq	in	AxiReadDmaReqType
dmaAck	out	AxiReadDmaAckType
swCache	in	slv ( 3 downto 0 ) := " 0000 "
axisMaster	out	AxiStreamMasterType
axisSlave	in	AxiStreamSlaveType
axisCtrl	in	AxiStreamCtrlType
axiReadMaster	out	AxiReadMasterType
axiReadSlave	in	AxiReadSlaveType

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDmaRead.vhd
• build/SRC_VHDL/surf/AxiStreamDmaRead.vhd