AxiStreamDmaRead.rtl Architecture Reference

Architecture >> AxiStreamDmaRead::rtl

Processes
comb	( axiReadSlave , axiRst , dmaReq , mMaster , mSlave , pause , r , sSlave , swCache )
seq	( axiClk )
Remap_mAxisMaster	( mMaster , r )
comb	( axiReadSlave , axiRst , dmaReq , mMaster , mSlave , pause , r , sSlave , swCache )
seq	( axiClk )
Remap_mAxisMaster	( mMaster , r )

Constants
DATA_BYTES_C	integer := AXIS_CONFIG_G.TDATA_BYTES_C
ADDR_LSB_C	integer := bitSize ( DATA_BYTES_C- 1 )
ARLEN_C	slv ( 7 downto 0 ) := getAxiLen ( AXI_CONFIG_G , 4096 )
REG_INIT_C	RegType := ( pendBytes = > ( others = > ' 0 ' ) , size = > ( others = > ' 0 ' ) , reqSize = > ( others = > ' 0 ' ) , reqCnt = > ( others = > ' 0 ' ) , ackCnt = > ( others = > ' 0 ' ) , dmaReq = > AXI_READ_DMA_REQ_INIT_C , dmaAck = > AXI_READ_DMA_ACK_INIT_C , shift = > ( others = > ' 0 ' ) , shiftEn = > ' 0 ' , first = > ' 0 ' , leftovers = > ' 0 ' , rMaster = > axiReadMasterInit ( AXI_CONFIG_G , AXI_BURST_G , AXI_CACHE_G ) , sMaster = > axiStreamMasterInit ( AXIS_CONFIG_G ) , reqState = > IDLE_S , state = > IDLE_S )

Types
ReqStateType	( IDLE_S , FIRST_S , NEXT_S )
StateType	( IDLE_S , MOVE_S , LAST_S , DONE_S , BLOWOFF_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
pause	sl
sSlave	AxiStreamSlaveType
pipeMaster	AxiStreamMasterType
pipeSlave	AxiStreamSlaveType
mMaster	AxiStreamMasterType
mSlave	AxiStreamSlaveType

Records
RegType

Instantiations
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_axistreamshift	AxiStreamShift <Entity AxiStreamShift>
u_pipeline	AxiStreamPipeline <Entity AxiStreamPipeline>
u_axistreamshift	AxiStreamShift <Entity AxiStreamShift>

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDmaRead.vhd
• build/SRC_VHDL/surf/AxiStreamDmaRead.vhd