AxiStreamDmaRingWrite Entity Reference

Inheritance diagram for AxiStreamDmaRingWrite:

Collaboration diagram for AxiStreamDmaRingWrite:

Entities
AxiStreamDmaRingWrite.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>
AxiStreamDmaRingPkg	Package <AxiStreamDmaRingPkg>

Generics
TPD_G	time := 1 ns
BUFFERS_G	natural range 2 to 64 := 64
BURST_SIZE_BYTES_G	natural range 4 to 2 ** 17 := 4096
ENABLE_UNALIGN_G	boolean := false
TRIGGER_USER_BIT_G	natural range 0 to 7 := 2
AXIL_BASE_ADDR_G	slv ( 31 downto 0 ) := ( others = > ' 0 ' )
DATA_AXIS_CONFIG_G	AxiStreamConfigType
STATUS_AXIS_CONFIG_G	AxiStreamConfigType
AXI_WRITE_CONFIG_G	AxiConfigType
FORCE_WRAP_ALIGN_G	boolean := false
BYP_SHIFT_G	boolean := true
BYP_CACHE_G	boolean := true

Ports
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
axisStatusClk	in	sl
axisStatusRst	in	sl
axisStatusMaster	out	AxiStreamMasterType
axisStatusSlave	in	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
axiClk	in	sl
axiRst	in	sl
axisDataMaster	in	AxiStreamMasterType
axisDataSlave	out	AxiStreamSlaveType
bufferClear	in	slv ( log2 ( BUFFERS_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
bufferClearEn	in	sl := ' 0 '
bufferEnabled	out	slv ( BUFFERS_G- 1 downto 0 )
bufferEmpty	out	slv ( BUFFERS_G- 1 downto 0 )
bufferFull	out	slv ( BUFFERS_G- 1 downto 0 )
bufferDone	out	slv ( BUFFERS_G- 1 downto 0 )
bufferTriggered	out	slv ( BUFFERS_G- 1 downto 0 )
bufferError	out	slv ( BUFFERS_G- 1 downto 0 )
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDmaRingWrite.vhd
• build/SRC_VHDL/surf/AxiStreamDmaRingWrite.vhd