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AxiStreamDmaRingWrite.rtl Architecture Reference
Architecture >> AxiStreamDmaRingWrite::rtl

Functions

slv   statusRamInit
slv   statusRamClear
slv   statusRamInit
slv   statusRamClear

Processes

comb  ( axiRst , axisDataMaster , bufferClear , bufferClearEn , dmaAck , endRamDout , modeRamDout , modeWrAddr , modeWrData , modeWrStrobe , modeWrValid , nextRamDout , r , startRamDout , statusRamDout , trigRamDout )
seq  ( axiClk )
comb  ( axiRst , axisDataMaster , bufferClear , bufferClearEn , dmaAck , endRamDout , modeRamDout , modeWrAddr , modeWrData , modeWrStrobe , modeWrValid , nextRamDout , r , startRamDout , statusRamDout , trigRamDout )
seq  ( axiClk )

Constants

RAM_DATA_WIDTH_C  integer := AXI_WRITE_CONFIG_G.ADDR_WIDTH_C
RAM_ADDR_WIDTH_C  integer := log2 ( BUFFERS_G )
AXIL_RAM_ADDR_WIDTH_C  integer := RAM_ADDR_WIDTH_C+ log2 ( ( RAM_DATA_WIDTH_C- 1 ) / 4 )
DMA_ADDR_LOW_C  integer := log2 ( BURST_SIZE_BYTES_G )
BURST_SIZE_SLV_C  slv ( 3 downto 0 ) := toSlv ( DMA_ADDR_LOW_C- 2 , 4 )
STATUS_RAM_INIT_C  slv ( 31 downto 0 ) := statusRamInit
AXIL_CONFIG_C  AxiLiteCrossbarMasterConfigArray := ( START_AXIL_C = > ( baseAddr = > getBufferAddr ( AXIL_BASE_ADDR_G , START_AXIL_C , 0 ) , addrBits = > AXIL_RAM_ADDR_WIDTH_C , connectivity = > X " FFFF " ) , END_AXIL_C = > ( baseAddr = > getBufferAddr ( AXIL_BASE_ADDR_G , END_AXIL_C , 0 ) , addrBits = > AXIL_RAM_ADDR_WIDTH_C , connectivity = > X " FFFF " ) , NEXT_AXIL_C = > ( baseAddr = > getBufferAddr ( AXIL_BASE_ADDR_G , NEXT_AXIL_C , 0 ) , addrBits = > AXIL_RAM_ADDR_WIDTH_C , connectivity = > X " FFFF " ) , TRIG_AXIL_C = > ( baseAddr = > getBufferAddr ( AXIL_BASE_ADDR_G , TRIG_AXIL_C , 0 ) , addrBits = > AXIL_RAM_ADDR_WIDTH_C , connectivity = > X " FFFF " ) , MODE_AXIL_C = > ( baseAddr = > getBufferAddr ( AXIL_BASE_ADDR_G , MODE_AXIL_C , 0 ) , addrBits = > RAM_ADDR_WIDTH_C+ 2 , connectivity = > X " FFFF " ) , STATUS_AXIL_C = > ( baseAddr = > getBufferAddr ( AXIL_BASE_ADDR_G , STATUS_AXIL_C , 0 ) , addrBits = > RAM_ADDR_WIDTH_C+ 2 , connectivity = > X " FFFF " ) )
INT_STATUS_AXIS_CONFIG_C  AxiStreamConfigType := ssiAxiStreamConfig ( 1 , TKEEP_FIXED_C , TUSER_FIRST_LAST_C , 4 )
REG_INIT_C  RegType := ( wrRamAddr = > ( others = > ' 0 ' ) , rdRamAddr = > ( others = > ' 0 ' ) , activeBuffer = > ( others = > ' 0 ' ) , ramWe = > ' 0 ' , statusClearEn = > ' 0 ' , statusClearAddr = > ( others = > ' 0 ' ) , nextAddr = > ( others = > ' 0 ' ) , startAddr = > ( others = > ' 0 ' ) , endAddr = > ( others = > ' 0 ' ) , trigAddr = > ( others = > ' 0 ' ) , mode = > ( others = > ' 0 ' ) , status = > ( others = > ' 0 ' ) , state = > WAIT_TVALID_S , dmaReq = > ( request = > ' 0 ' , drop = > ' 0 ' , address = > ( others = > ' 0 ' ) , maxSize = > toSlv ( BURST_SIZE_BYTES_G , 32 ) , prot = > ( others = > ' 0 ' ) ) , trigger = > ' 0 ' , softTrigger = > ( others = > ' 0 ' ) , eofe = > ' 0 ' , bufferEnabled = > ( others = > ' 0 ' ) , bufferEmpty = > ( others = > ' 1 ' ) , bufferFull = > ( others = > ' 0 ' ) , bufferDone = > ( others = > ' 1 ' ) , bufferTriggered = > ( others = > ' 0 ' ) , bufferError = > ( others = > ' 0 ' ) , bufferClear = > ( others = > ' 0 ' ) , axisStatusMaster = > axiStreamMasterInit ( INT_STATUS_AXIS_CONFIG_C ) )

Types

StateType  ( WAIT_TVALID_S , ASSERT_ADDR_S , LATCH_POINTERS_S , WAIT_DMA_DONE_S )

Signals

locAxilWriteMasters  AxiLiteWriteMasterArray ( AXIL_MASTERS_C- 1 downto 0 )
locAxilWriteSlaves  AxiLiteWriteSlaveArray ( AXIL_MASTERS_C- 1 downto 0 )
locAxilReadMasters  AxiLiteReadMasterArray ( AXIL_MASTERS_C- 1 downto 0 )
locAxilReadSlaves  AxiLiteReadSlaveArray ( AXIL_MASTERS_C- 1 downto 0 )
r  RegType := REG_INIT_C
rin  RegType
dmaAck  AxiWriteDmaAckType
startRamDout  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
endRamDout  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
nextRamDout  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
trigRamDout  slv ( RAM_DATA_WIDTH_C- 1 downto 0 )
modeRamDout  slv ( 31 downto 0 )
statusRamDout  slv ( 31 downto 0 )
modeWrValid  sl
modeWrStrobe  slv ( 3 downto 0 )
modeWrAddr  slv ( RAM_ADDR_WIDTH_C- 1 downto 0 )
modeWrData  slv ( 31 downto 0 )
statusWe  sl
statusAddr  slv ( RAM_ADDR_WIDTH_C- 1 downto 0 )
statusDin  slv ( 31 downto 0 )

Records

RegType 

Instantiations

u_axilitecrossbar_1  AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_axidualportram_start  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_end  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_next  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_trigger  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_mode  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_status  AxiDualPortRam <Entity AxiDualPortRam>
u_axistreamdmawrite_1  AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_axistreamfifo_msg  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_axilitecrossbar_1  AxiLiteCrossbar <Entity AxiLiteCrossbar>
u_axidualportram_start  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_end  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_next  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_trigger  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_mode  AxiDualPortRam <Entity AxiDualPortRam>
u_axidualportram_status  AxiDualPortRam <Entity AxiDualPortRam>
u_axistreamdmawrite_1  AxiStreamDmaWrite <Entity AxiStreamDmaWrite>
u_axistreamfifo_msg  AxiStreamFifoV2 <Entity AxiStreamFifoV2>
The documentation for this design unit was generated from the following files: