AxiDualPortRam Entity Reference

Inheritance diagram for AxiDualPortRam:

Collaboration diagram for AxiDualPortRam:

Entities
AxiDualPortRam.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
MEMORY_INIT_FILE_G	string := " none "
MEMORY_INIT_PARAM_G	string := " 0 "
READ_LATENCY_G	natural range 0 to 3 := 2
AXI_WR_EN_G	boolean := true
SYS_WR_EN_G	boolean := false
SYS_BYTE_WR_EN_G	boolean := false
COMMON_CLK_G	boolean := false
ADDR_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 5
DATA_WIDTH_G	integer := 32
INIT_G	slv := " 0 "

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
clk	in	sl := ' 0 '
en	in	sl := ' 1 '
we	in	sl := ' 0 '
weByte	in	slv ( wordCount ( DATA_WIDTH_G , 8 ) - 1 downto 0 ) := ( others = > ' 0 ' )
rst	in	sl := ' 0 '
addr	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
din	in	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dout	out	slv ( DATA_WIDTH_G- 1 downto 0 )
axiWrValid	out	sl
axiWrStrobe	out	slv ( wordCount ( DATA_WIDTH_G , 8 ) - 1 downto 0 )
axiWrAddr	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
axiWrData	out	slv ( DATA_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiDualPortRam.vhd
• build/SRC_VHDL/surf/AxiDualPortRam.vhd