AxiDualPortRam.rtl Architecture Reference

Architecture >> AxiDualPortRam::rtl

Processes
comb	( axiDout , axiReadMaster , axiRst , axiWriteMaster , r )
seq	( axiClk , axiRst )
REG	( clk , rst )
comb	( axiDout , axiReadMaster , axiRst , axiWriteMaster , r )
seq	( axiClk , axiRst )
REG	( clk , rst )

Constants
AXI_DEC_BITS_C	integer := ite ( DATA_WIDTH_G< = 32 , 0 , log2 ( ( DATA_WIDTH_G- 1 ) / 32 ) )
AXI_DEC_ADDR_HIGH_C	integer := 1 + AXI_DEC_BITS_C
AXI_DEC_ADDR_LOW_C	integer := 2
AXI_RAM_ADDR_HIGH_C	integer := ADDR_WIDTH_G+ AXI_DEC_ADDR_RANGE_C ' high
AXI_RAM_ADDR_LOW_C	integer := AXI_DEC_ADDR_RANGE_C ' high+ 1
ADDR_AXI_WORDS_C	natural := wordCount ( DATA_WIDTH_G , 32 )
ADDR_AXI_BYTES_C	natural := wordCount ( DATA_WIDTH_G , 8 )
RAM_WIDTH_C	natural := ADDR_AXI_WORDS_C* 32
STRB_WIDTH_C	natural := minimum ( 4 , ADDR_AXI_BYTES_C )
REG_INIT_C	RegType := ( axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiAddr = > ( others = > ' 0 ' ) , axiWrStrobe = > ( others = > ' 0 ' ) , rdLatecy = > 0 , state = > IDLE_S )

Types
StateType	( IDLE_S , RD_S )

Subtypes
AXI_DEC_ADDR_RANGE_C	integer range AXI_DEC_ADDR_HIGH_C downto AXI_DEC_ADDR_LOW_C
AXI_RAM_ADDR_RANGE_C	integer range AXI_RAM_ADDR_HIGH_C downto AXI_RAM_ADDR_LOW_C

Signals
r	RegType := REG_INIT_C
rin	RegType
axiWrDataFanout	slv ( RAM_WIDTH_C- 1 downto 0 )
axiDout	slv ( RAM_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
axiSyncWrEn	sl
axiSyncIn	slv ( DATA_WIDTH_G+ ADDR_WIDTH_G+ ADDR_AXI_BYTES_C- 1 downto 0 )
axiSyncOut	slv ( DATA_WIDTH_G+ ADDR_WIDTH_G+ ADDR_AXI_BYTES_C- 1 downto 0 )
weByteMask	slv ( wordCount ( DATA_WIDTH_G , 8 ) - 1 downto 0 )
doutInt	slv ( DATA_WIDTH_G- 1 downto 0 )

Records
RegType

Instantiations
u_ram	TrueDualPortRamXpm <Entity TrueDualPortRamXpm>
u_ram	TrueDualPortRamAlteraMf <Entity TrueDualPortRamAlteraMf>
dualportram_1	DualPortRam <Entity DualPortRam>
dualportram_1	DualPortRam <Entity DualPortRam>
u_truedualportram_1	TrueDualPortRam <Entity TrueDualPortRam>
u_synchronizerfifo_1	SynchronizerFifo <Entity SynchronizerFifo>
u_ram	TrueDualPortRamXpm <Entity TrueDualPortRamXpm>
u_ram	TrueDualPortRamAlteraMf <Entity TrueDualPortRamAlteraMf>
dualportram_1	DualPortRam <Entity DualPortRam>
dualportram_1	DualPortRam <Entity DualPortRam>
u_truedualportram_1	TrueDualPortRam <Entity TrueDualPortRam>
u_synchronizerfifo_1	SynchronizerFifo <Entity SynchronizerFifo>

---

The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiDualPortRam.vhd
• build/SRC_VHDL/surf/AxiDualPortRam.vhd