TrueDualPortRam Entity Reference

Inheritance diagram for TrueDualPortRam:

Entities
TrueDualPortRam.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
DOA_REG_G	boolean := false
DOB_REG_G	boolean := false
MODE_G	string := " read-first "
BYTE_WR_EN_G	boolean := false
DATA_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 18
BYTE_WIDTH_G	integer := 8
ADDR_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 9
INIT_G	slv := " 0 "

Ports
clka	in	sl := ' 0 '
ena	in	sl := ' 1 '
wea	in	sl := ' 0 '
weaByte	in	slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
rsta	in	sl := not ( RST_POLARITY_G )
addra	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dina	in	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
douta	out	slv ( DATA_WIDTH_G- 1 downto 0 )
regcea	in	sl := ' 1 '
clkb	in	sl := ' 0 '
enb	in	sl := ' 1 '
web	in	sl := ' 0 '
webByte	in	slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
rstb	in	sl := not ( RST_POLARITY_G )
addrb	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dinb	in	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutb	out	slv ( DATA_WIDTH_G- 1 downto 0 )
regceb	in	sl := ' 1 '

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The documentation for this design unit was generated from the following files:

• base/ram/inferred/TrueDualPortRam.vhd
• build/SRC_VHDL/surf/TrueDualPortRam.vhd