TrueDualPortRam.rtl Architecture Reference

Architecture >> TrueDualPortRam::rtl

Processes
PROCESS_55	( clka )
PROCESS_56	( clka , rsta )
PROCESS_57	( clkb )
PROCESS_58	( clkb , rstb )
PROCESS_59	( clka , rsta )
PROCESS_60	( clkb , rstb )
PROCESS_61	( clka , rsta )
PROCESS_62	( clkb , rstb )
PROCESS_63	( clka , rsta )
PROCESS_64	( clkb , rstb )
PROCESS_180	( clka )
PROCESS_181	( clka , rsta )
PROCESS_182	( clkb )
PROCESS_183	( clkb , rstb )
PROCESS_184	( clka , rsta )
PROCESS_185	( clkb , rstb )
PROCESS_186	( clka , rsta )
PROCESS_187	( clkb , rstb )
PROCESS_188	( clka , rsta )
PROCESS_189	( clkb , rstb )

Constants
BYTE_WIDTH_C	natural := ite ( BYTE_WR_EN_G , BYTE_WIDTH_G , DATA_WIDTH_G )
NUM_BYTES_C	natural := wordCount ( DATA_WIDTH_G , BYTE_WIDTH_C )
FULL_DATA_WIDTH_C	natural := NUM_BYTES_C* BYTE_WIDTH_C
INIT_C	slv ( FULL_DATA_WIDTH_C- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( FULL_DATA_WIDTH_C ) , INIT_G )

Types
MemType	( ( 2 ** ADDR_WIDTH_G ) - 1 downto 0 ) slv ( FULL_DATA_WIDTH_C- 1 downto 0 )

Signals
doutAInt	slv ( FULL_DATA_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
doutBInt	slv ( FULL_DATA_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
weaByteInt	slv ( weaByte ) := ( others = > ' 0 ' )
webByteInt	slv ( webByte ) := ( others = > ' 0 ' )

Attributes
ram_style	string
ram_style	variable is " block "
ram_extract	string
ram_extract	variable is " TRUE "
keep	boolean
keep	variable is true
syn_ramstyle	string
syn_ramstyle	variable is " block "
syn_keep	string
syn_keep	variable is " TRUE "

Shared Variables
mem	shared MemType := := ( others = > INIT_C )

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The documentation for this design unit was generated from the following files:

• base/ram/inferred/TrueDualPortRam.vhd
• build/SRC_VHDL/surf/TrueDualPortRam.vhd