Architecture >> TrueDualPortRam::rtl

Functions
string	toXpmWriteMode ( mode: in string )

Constants
READ_LATENCY_A_BASE_C	natural := ite ( READ_LATENCY_A_G< 0 , READ_LATENCY_G , READ_LATENCY_A_G )
READ_LATENCY_B_BASE_C	natural := ite ( READ_LATENCY_B_G< 0 , READ_LATENCY_G , READ_LATENCY_B_G )
READ_LATENCY_A_C	natural := ite ( DOA_REG_Gand ( READ_LATENCY_A_BASE_C = 1 ) , 2 , READ_LATENCY_A_BASE_C )
READ_LATENCY_B_C	natural := ite ( DOB_REG_Gand ( READ_LATENCY_B_BASE_C = 1 ) , 2 , READ_LATENCY_B_BASE_C )
READ_LATENCY_C	natural := ite ( READ_LATENCY_A_C> READ_LATENCY_B_C , READ_LATENCY_A_C , READ_LATENCY_B_C )
DOA_REG_C	boolean := ( READ_LATENCY_A_C = 2 )
DOB_REG_C	boolean := ( READ_LATENCY_B_C = 2 )
WRITE_MODE_C	string := toXpmWriteMode ( MODE_G )

Signals
weaVector	slv ( ite ( BYTE_WR_EN_G , wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) , 1 ) - 1 downto 0 )
webVector	slv ( ite ( BYTE_WR_EN_G , wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) , 1 ) - 1 downto 0 )

Instantiations
u_ram	TrueDualPortRamXpm <Entity TrueDualPortRamXpm>
u_ram	TrueDualPortRamAlteraMf <Entity TrueDualPortRamAlteraMf>
u_ram	TrueDualPortRamInferred <Entity TrueDualPortRamInferred>

The documentation for this design unit was generated from the following file:

Functions

Constants