TrueDualPortRamAlteraMf Entity Reference

Inheritance diagram for TrueDualPortRamAlteraMf:

Entities
TrueDualPortRamAlteraMf.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
COMMON_CLK_G	boolean := false
RST_POLARITY_G	sl := ' 1 '
MEMORY_TYPE_G	string := " block "
READ_LATENCY_G	natural range 0 to 100 := 1
DATA_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 16
BYTE_WR_EN_G	boolean := false
BYTE_WIDTH_G	integer range 8 to 9 := 8
ADDR_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 4

Ports
clka	in	sl := ' 0 '
ena	in	sl := ' 1 '
wea	in	slv ( ite ( BYTE_WR_EN_G , wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) , 1 ) - 1 downto 0 ) := ( others = > ' 0 ' )
regcea	in	sl := ' 1 '
rsta	in	sl := not ( RST_POLARITY_G )
addra	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dina	in	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
douta	out	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
clkb	in	sl := ' 0 '
enb	in	sl := ' 1 '
web	in	slv ( ite ( BYTE_WR_EN_G , wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) , 1 ) - 1 downto 0 ) := ( others = > ' 0 ' )
regceb	in	sl := ' 1 '
rstb	in	sl := not ( RST_POLARITY_G )
addrb	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dinb	in	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutb	out	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )

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The documentation for this design unit was generated from the following files:

• base/ram/dummy/TrueDualPortRamXpmAlteraMfDummy.vhd
• build/SRC_VHDL/surf/TrueDualPortRamXpmAlteraMfDummy.vhd