AxiLiteCrossbar Entity Reference

Inheritance diagram for AxiLiteCrossbar:

Entities
AxiLiteCrossbar.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
ArbiterPkg	Package <ArbiterPkg>
TextUtilPkg	Package <TextUtilPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
NUM_SLAVE_SLOTS_G	natural range 1 to 16 := 4
NUM_MASTER_SLOTS_G	natural range 1 to 64 := 4
DEC_ERROR_RESP_G	slv ( 1 downto 0 ) := AXI_RESP_DECERR_C
MASTERS_CONFIG_G	AxiLiteCrossbarMasterConfigArray := AXIL_XBAR_CFG_DEFAULT_C
DEBUG_G	boolean := false

Ports
axiClk	in	sl
axiClkRst	in	sl
sAxiWriteMasters	in	AxiLiteWriteMasterArray ( NUM_SLAVE_SLOTS_G- 1 downto 0 )
sAxiWriteSlaves	out	AxiLiteWriteSlaveArray ( NUM_SLAVE_SLOTS_G- 1 downto 0 )
sAxiReadMasters	in	AxiLiteReadMasterArray ( NUM_SLAVE_SLOTS_G- 1 downto 0 )
sAxiReadSlaves	out	AxiLiteReadSlaveArray ( NUM_SLAVE_SLOTS_G- 1 downto 0 )
mAxiWriteMasters	out	AxiLiteWriteMasterArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )
mAxiWriteSlaves	in	AxiLiteWriteSlaveArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )
mAxiReadMasters	out	AxiLiteReadMasterArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )
mAxiReadSlaves	in	AxiLiteReadSlaveArray ( NUM_MASTER_SLOTS_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteCrossbar.vhd
• build/SRC_VHDL/surf/AxiLiteCrossbar.vhd