AxiLiteCrossbar.rtl Architecture Reference

Architecture >> AxiLiteCrossbar::rtl

Processes
comb	( axiClkRst , mAxiReadSlaves , mAxiWriteSlaves , r , sAxiReadMasters , sAxiWriteMasters )
seq	( axiClk , axiClkRst )
comb	( axiClkRst , mAxiReadSlaves , mAxiWriteSlaves , r , sAxiReadMasters , sAxiWriteMasters )
seq	( axiClk , axiClkRst )

Constants
REQ_NUM_SIZE_C	integer := bitSize ( NUM_MASTER_SLOTS_G- 1 )
ACK_NUM_SIZE_C	integer := bitSize ( NUM_SLAVE_SLOTS_G- 1 )
REG_INIT_C	RegType := ( slave = > ( others = > ( wrState = > S_WAIT_AXI_TXN_S , wrReqs = > ( others = > ' 0 ' ) , wrReqNum = > ( others = > ' 0 ' ) , rdState = > S_WAIT_AXI_TXN_S , rdReqs = > ( others = > ' 0 ' ) , rdReqNum = > ( others = > ' 0 ' ) ) ) , master = > ( others = > ( wrState = > M_WAIT_REQ_S , wrAcks = > ( others = > ' 0 ' ) , wrAckNum = > ( others = > ' 0 ' ) , wrValid = > ' 0 ' , rdState = > M_WAIT_REQ_S , rdAcks = > ( others = > ' 0 ' ) , rdAckNum = > ( others = > ' 0 ' ) , rdValid = > ' 0 ' ) ) , sAxiWriteSlaves = > ( others = > AXI_LITE_WRITE_SLAVE_INIT_C ) , sAxiReadSlaves = > ( others = > AXI_LITE_READ_SLAVE_INIT_C ) , mAxiWriteMasters = > axiWriteMasterInit ( MASTERS_CONFIG_G ) , mAxiReadMasters = > axiReadMasterInit ( MASTERS_CONFIG_G ) )

Types
SlaveStateType	( S_WAIT_AXI_TXN_S , S_DEC_ERR_S , S_ACK_S , S_TXN_S )
SlaveArray	array ( natural range <> ) of SlaveType
MasterStateType	( M_WAIT_REQ_S , M_WAIT_READYS_S , M_WAIT_REQ_FALL_S )
MasterArray	array ( natural range <> ) of MasterType
AxiStatusArray	array ( natural range <> ) of AxiLiteStatusType

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
SlaveType
MasterType
RegType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteCrossbar.vhd
• build/SRC_VHDL/surf/AxiLiteCrossbar.vhd