AxiStreamDmaWrite Entity Reference

Inheritance diagram for AxiStreamDmaWrite:

Collaboration diagram for AxiStreamDmaWrite:

Entities
AxiStreamDmaWrite.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiPkg	Package <AxiPkg>
AxiDmaPkg	Package <AxiDmaPkg>

Generics
TPD_G	time := 1 ns
AXI_READY_EN_G	boolean := false
AXIS_CONFIG_G	AxiStreamConfigType
AXI_CONFIG_G	AxiConfigType
AXI_BURST_G	slv ( 1 downto 0 ) := " 01 "
AXI_CACHE_G	slv ( 3 downto 0 ) := " 1111 "
BURST_BYTES_G	positive range 1 to 4096 := 4096
SW_CACHE_EN_G	boolean := false
ACK_WAIT_BVALID_G	boolean := true
PIPE_STAGES_G	natural := 1
BYP_SHIFT_G	boolean := false
BYP_CACHE_G	boolean := false

Ports
axiClk	in	sl
axiRst	in	sl
dmaReq	in	AxiWriteDmaReqType
dmaAck	out	AxiWriteDmaAckType
swCache	in	slv ( 3 downto 0 ) := " 0000 "
axisMaster	in	AxiStreamMasterType
axisSlave	out	AxiStreamSlaveType
axiWriteMaster	out	AxiWriteMasterType
axiWriteSlave	in	AxiWriteSlaveType
axiWriteCtrl	in	AxiCtrlType := AXI_CTRL_UNUSED_C

---

The documentation for this design unit was generated from the following files:

• axi/dma/rtl/v1/AxiStreamDmaWrite.vhd
• build/SRC_VHDL/surf/AxiStreamDmaWrite.vhd