Architecture >> AxiStreamDmaWrite::rtl

Processes
comb	( axiRst , axiWriteSlave , cache , dmaReq , intAxisMaster , lastDet , pause , r , swCache )
seq	( axiClk )
comb	( axiRst , axiWriteSlave , cache , dmaReq , intAxisMaster , lastDet , pause , r , swCache )
seq	( axiClk )

Constants
LOC_AXIS_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > AXIS_CONFIG_G.TSTRB_EN_C , TDATA_BYTES_C = > AXIS_CONFIG_G.TDATA_BYTES_C , TDEST_BITS_C = > AXIS_CONFIG_G.TDEST_BITS_C , TID_BITS_C = > AXIS_CONFIG_G.TID_BITS_C , TKEEP_MODE_C = > TKEEP_NORMAL_C , TUSER_BITS_C = > AXIS_CONFIG_G.TUSER_BITS_C , TUSER_MODE_C = > TUSER_NORMAL_C )
DATA_BYTES_C	integer := LOC_AXIS_CONFIG_C.TDATA_BYTES_C
ADDR_LSB_C	integer := bitSize ( DATA_BYTES_C- 1 )
AWLEN_C	slv ( 7 downto 0 ) := getAxiLen ( AXI_CONFIG_G , BURST_BYTES_G )
FIFO_ADDR_WIDTH_C	natural := ite ( ( AXI_CONFIG_G.LEN_BITS_C< 3 ) , 4 , ( AXI_CONFIG_G.LEN_BITS_C+ 1 ) )
REG_INIT_C	RegType := ( dmaReq = > AXI_WRITE_DMA_REQ_INIT_C , dmaAck = > AXI_WRITE_DMA_ACK_INIT_C , threshold = > ( others = > ' 1 ' ) , shift = > ( others = > ' 0 ' ) , shiftEn = > ' 0 ' , first = > ' 0 ' , last = > ' 0 ' , reqCount = > ( others = > ' 0 ' ) , ackCount = > ( others = > ' 0 ' ) , stCount = > ( others = > ' 0 ' ) , awlen = > ( others = > ' 0 ' ) , wMaster = > axiWriteMasterInit ( AXI_CONFIG_G , ' 1 ' , AXI_BURST_G , AXI_CACHE_G ) , slave = > AXI_STREAM_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , FIRST_S , NEXT_S , MOVE_S , DUMP_S , WAIT_S , DONE_S )

Records
RegType

Instantiations
u_axistreamshift	AxiStreamShift <Entity AxiStreamShift>
u_cache	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_last	FifoSync <Entity FifoSync>
u_axistreamshift	AxiStreamShift <Entity AxiStreamShift>
u_cache	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_last	FifoSync <Entity FifoSync>

The documentation for this design unit was generated from the following files:

Processes

Constants