FifoSync Entity Reference

Inheritance diagram for FifoSync:

Collaboration diagram for FifoSync:

Entities
FifoSync.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
MEMORY_TYPE_G	string := " block "
BYP_RAM_G	boolean := false
FWFT_EN_G	boolean := false
PIPE_STAGES_G	natural := 0
DATA_WIDTH_G	positive := 16
ADDR_WIDTH_G	positive := 4
INIT_G	slv := " 0 "
FULL_THRES_G	positive := 1
EMPTY_THRES_G	positive := 1

Ports
rst	in	sl := not RST_POLARITY_G
clk	in	sl
wr_en	in	sl
rd_en	in	sl
din	in	slv ( DATA_WIDTH_G- 1 downto 0 )
dout	out	slv ( DATA_WIDTH_G- 1 downto 0 )
data_count	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
wr_ack	out	sl
valid	out	sl
overflow	out	sl
underflow	out	sl
prog_full	out	sl
prog_empty	out	sl
almost_full	out	sl
almost_empty	out	sl
full	out	sl
not_full	out	sl
empty	out	sl

---

The documentation for this design unit was generated from the following files:

• base/fifo/rtl/inferred/FifoSync.vhd
• build/SRC_VHDL/surf/FifoSync.vhd