FifoSync.mapping Architecture Reference

Architecture >> FifoSync::mapping

Signals
rdRdy	sl := ' 0 '
rdIndex	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
wrRdy	sl := ' 0 '
wrIndex	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
wea	sl := ' 0 '
addra	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dina	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
addrb	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutb	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
enb	sl := ' 0 '
regceb	sl := ' 0 '
localDout	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
localValid	sl := ' 0 '
localRdEn	sl := ' 0 '

Instantiations
u_wr_fsm	FifoWrFsm <Entity FifoWrFsm>
u_rd_fsm	FifoRdFsm <Entity FifoRdFsm>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_pipeline	FifoOutputPipeline <Entity FifoOutputPipeline>
u_wr_fsm	FifoWrFsm <Entity FifoWrFsm>
u_rd_fsm	FifoRdFsm <Entity FifoRdFsm>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
u_pipeline	FifoOutputPipeline <Entity FifoOutputPipeline>

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/inferred/FifoSync.vhd
• build/SRC_VHDL/surf/FifoSync.vhd