SimpleDualPortRam Entity Reference

Inheritance diagram for SimpleDualPortRam:

Collaboration diagram for SimpleDualPortRam:

Entities
SimpleDualPortRam.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
MEMORY_TYPE_G	string := " block "
DOB_REG_G	boolean := false
BYTE_WR_EN_G	boolean := false
DATA_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 16
BYTE_WIDTH_G	integer := 8
ADDR_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 4
INIT_G	slv := " 0 "
SYNTH_MODE_G	string := " inferred "
COMMON_CLK_G	boolean := false
MEMORY_INIT_FILE_G	string := " none "
MEMORY_INIT_PARAM_G	string := " 0 "
READ_LATENCY_G	natural range 0 to 100 := 1

Ports
clka	in	sl := ' 0 '
ena	in	sl := ' 1 '
wea	in	sl := ' 0 '
weaByte	in	slv ( wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) - 1 downto 0 ) := ( others = > ' 0 ' )
addra	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
dina	in	slv ( DATA_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
clkb	in	sl := ' 0 '
enb	in	sl := ' 1 '
regceb	in	sl := ' 1 '
rstb	in	sl := not ( RST_POLARITY_G )
addrb	in	slv ( ADDR_WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
doutb	out	slv ( DATA_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following file:

• base/ram/rtl/SimpleDualPortRam.vhd