SimpleDualPortRam.rtl Architecture Reference

Architecture >> SimpleDualPortRam::rtl

Components
SimpleDualPortRamInferred	<Entity SimpleDualPortRamInferred>
SimpleDualPortRamXpm	<Entity SimpleDualPortRamXpm>
SimpleDualPortRamAlteraMf	<Entity SimpleDualPortRamAlteraMf>

Constants
DOB_REG_C	boolean := DOB_REG_Gor ( READ_LATENCY_G = 2 )
READ_LATENCY_C	natural := ite ( DOB_REG_Cand READ_LATENCY_G = 1 , 2 , READ_LATENCY_G )

Signals
weaVector	slv ( ite ( BYTE_WR_EN_G , wordCount ( DATA_WIDTH_G , BYTE_WIDTH_G ) , 1 ) - 1 downto 0 )

Instantiations
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRamInferred <Entity SimpleDualPortRamInferred>

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The documentation for this design unit was generated from the following file:

• base/ram/rtl/SimpleDualPortRam.vhd