FifoOutputPipeline Entity Reference

Inheritance diagram for FifoOutputPipeline:

Entities
FifoOutputPipeline.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
DATA_WIDTH_G	integer range 1 to ( 2 ** 24 ) := 16
PIPE_STAGES_G	natural range 0 to 16 := 1

Ports
sData	in	slv ( DATA_WIDTH_G- 1 downto 0 )
sValid	in	sl
sRdEn	out	sl
mData	out	slv ( DATA_WIDTH_G- 1 downto 0 )
mValid	out	sl
mRdEn	in	sl
clk	in	sl
rst	in	sl := not RST_POLARITY_G

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/FifoOutputPipeline.vhd
• build/SRC_VHDL/surf/FifoOutputPipeline.vhd