FifoOutputPipeline.rtl Architecture Reference

Architecture >> FifoOutputPipeline::rtl

Processes
comb	( mRdEn , r , rst , sData , sValid )
seq	( clk , rst )
comb	( mRdEn , r , rst , sData , sValid )
seq	( clk , rst )

Constants
PIPE_STAGES_C	natural := PIPE_STAGES_G+ 1
REG_INIT_C	RegType := ( sRdEn = > ' 0 ' , mValid = > ( others = > ' 0 ' ) , mData = > ( others = > ( others = > ' 0 ' ) ) )

Types
DataArray	array ( natural range <> ) of slv ( DATA_WIDTH_G- 1 downto 0 )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/FifoOutputPipeline.vhd
• build/SRC_VHDL/surf/FifoOutputPipeline.vhd