FifoWrFsm Entity Reference

Inheritance diagram for FifoWrFsm:

Entities
FifoWrFsm.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
FIFO_ASYNC_G	boolean := false
DATA_WIDTH_G	positive := 16
ADDR_WIDTH_G	positive := 4
FULL_THRES_G	positive := 1

Ports
rst	in	sl
rdRdy	in	sl
rdIndex	in	slv ( ADDR_WIDTH_G- 1 downto 0 )
wrRdy	out	sl
wrIndex	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
wea	out	sl
addra	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
dina	out	slv ( DATA_WIDTH_G- 1 downto 0 )
wr_clk	in	sl
wr_en	in	sl
din	in	slv ( DATA_WIDTH_G- 1 downto 0 )
wr_data_count	out	slv ( ADDR_WIDTH_G- 1 downto 0 )
wr_ack	out	sl
overflow	out	sl
prog_full	out	sl
almost_full	out	sl
full	out	sl
not_full	out	sl

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The documentation for this design unit was generated from the following files:

• base/fifo/rtl/inferred/FifoWrFsm.vhd
• build/SRC_VHDL/surf/FifoWrFsm.vhd